Verilog问题# JobHunting - 待字闺中
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最近在准备Verilog的问题的时候发现这题：
Difference between inter statement and intra statement delay?
//define register variables
reg a, b, c;
//intra assignment delays
initial
begin
a = 0; c = 0;
b = #5 a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time units to assign value
//to b.
end
//Equivalent method with temporary variables and regular delay control
initial
begin
a = 0; c = 0;
temp_ac = a + c;
#5 b = temp_ac; //Take value of a + c at the current time and
//store it in a temporary variable. Even though a and c
//might change between 0 and 5,
//the value assigned to b at time 5 is unaffected.
end
求解释一个这个verilog的问题。还是没看懂这两个有什么区别，好像两个都是在0的时
候就把a+c算好了，0~5变化也不会影响b啊~~
还有一些附加的问题：
1、What is delta simulation time?（找不到答案。。。用verilog/VHDL的时候也没
听过。。。掩面）
2、Difference between task and function? （task 和function在verilog实际中用
的多么？verilog我只是用CMOS VLSI DESIGN后面的appendix学过，没看到用这两个的
例子，VHDL有hands-on experiences但印象中也没这个）
Difference between inter statement and intra statement delay?
//define register variables
reg a, b, c;
//intra assignment delays
initial
begin
a = 0; c = 0;
b = #5 a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time units to assign value
//to b.
end
//Equivalent method with temporary variables and regular delay control
initial
begin
a = 0; c = 0;
temp_ac = a + c;
#5 b = temp_ac; //Take value of a + c at the current time and
//store it in a temporary variable. Even though a and c
//might change between 0 and 5,
//the value assigned to b at time 5 is unaffected.
end
求解释一个这个verilog的问题。还是没看懂这两个有什么区别，好像两个都是在0的时
候就把a+c算好了，0~5变化也不会影响b啊~~
还有一些附加的问题：
1、What is delta simulation time?（找不到答案。。。用verilog/VHDL的时候也没
听过。。。掩面）
2、Difference between task and function? （task 和function在verilog实际中用
的多么？verilog我只是用CMOS VLSI DESIGN后面的appendix学过，没看到用这两个的
例子，VHDL有hands-on experiences但印象中也没这个）
