马路中间出了个大旋涡# Joke - 肚皮舞运动
h*3
1 楼
The company is a very stable fabless company. The company offers
comprehensive package including competitive base salary, annual bonus and
RSU grants. Both positions are in San Jose, CA.
PM me if you are interested.
1. Sr. Engineer, Video Architecture/Modeling
RESPONSIBILITIES
- Develop architecture for the hardware implementation of video codec,
including H.264, VP8 and new H.265/HEVC
- Design, implement and maintain video codec functional models for the
hardware implementation
- Support hardware team for RTL implementation
- Support firmware team for firmware development, debug and integration
- Develop tests and test plan to verify the correctness of the hardware
design
REQUIREMENTS
- BS/MS/PHD in EE, CS or CE with 5+ years of experiences with architecture
and/or modeling
- Language: C/C++, scripting language
- Thorough knowledge of video standards such as H.264 and/or VP8
- Knowledge of new H.265/HEVC standard a big plus
- Experience of SystemC, Verilog/SystemVerilog a plus
- Experience and understanding of MIPS and/or ARM CPU architecture a plus
2. Sr. Engineer, ASIC Design/Verification
RESPONSIBILITIES
- ASIC implementation of H.265/HEVC video codec blocks
- Micro-architecture design and documentation
- RTL coding, simulation and ASIC block debug
- Test plan development, direct and/or random based design verification
- Functional block c-modeling, firmware integration
- Synthesis, Timing and Formal
REQUIREMENTS
- BS/MS/PHD in EE, CS or CE with 5+ years of experiences with design and/or
verification
- Industrial experience in the design/verification of video ASICs
- Knowledge of video codec standards such as H.264, MPEG-2 or VP8
- Knowledge of new H.265/HEVC standard a big plus
- Language: Verilog/VHDL, SystemVerilog, C/C++/SystemC, Scripting language
- Tools: NCVerilog, DC, LEC, Spyglass, etc.
comprehensive package including competitive base salary, annual bonus and
RSU grants. Both positions are in San Jose, CA.
PM me if you are interested.
1. Sr. Engineer, Video Architecture/Modeling
RESPONSIBILITIES
- Develop architecture for the hardware implementation of video codec,
including H.264, VP8 and new H.265/HEVC
- Design, implement and maintain video codec functional models for the
hardware implementation
- Support hardware team for RTL implementation
- Support firmware team for firmware development, debug and integration
- Develop tests and test plan to verify the correctness of the hardware
design
REQUIREMENTS
- BS/MS/PHD in EE, CS or CE with 5+ years of experiences with architecture
and/or modeling
- Language: C/C++, scripting language
- Thorough knowledge of video standards such as H.264 and/or VP8
- Knowledge of new H.265/HEVC standard a big plus
- Experience of SystemC, Verilog/SystemVerilog a plus
- Experience and understanding of MIPS and/or ARM CPU architecture a plus
2. Sr. Engineer, ASIC Design/Verification
RESPONSIBILITIES
- ASIC implementation of H.265/HEVC video codec blocks
- Micro-architecture design and documentation
- RTL coding, simulation and ASIC block debug
- Test plan development, direct and/or random based design verification
- Functional block c-modeling, firmware integration
- Synthesis, Timing and Formal
REQUIREMENTS
- BS/MS/PHD in EE, CS or CE with 5+ years of experiences with design and/or
verification
- Industrial experience in the design/verification of video ASICs
- Knowledge of video codec standards such as H.264, MPEG-2 or VP8
- Knowledge of new H.265/HEVC standard a big plus
- Language: Verilog/VHDL, SystemVerilog, C/C++/SystemC, Scripting language
- Tools: NCVerilog, DC, LEC, Spyglass, etc.
