Re: chip 里面的transmission line effect# EE - 电子工程
Y*t
1 楼
Depends on what level you are working on.
If you are designing on-chip ckts, there is only one way,
that is the first solution. First, we know we don't have to
treat the wiring as transmission line. Secondly, the
solution 2 is too time consuming. Nowadays, there's
millions of gates in a single chip. How many wiring is
there? How long will the solution 2 take in simulation?
The simulation time will kill the project. In chip ckt
design, the timing is calcuated by using a polynomial, with
th
If you are designing on-chip ckts, there is only one way,
that is the first solution. First, we know we don't have to
treat the wiring as transmission line. Secondly, the
solution 2 is too time consuming. Nowadays, there's
millions of gates in a single chip. How many wiring is
there? How long will the solution 2 take in simulation?
The simulation time will kill the project. In chip ckt
design, the timing is calcuated by using a polynomial, with
th