请教一个VERILOG的问题# EE - 电子工程
s*y
1 楼
在修改一个别人写的状态机。
always @ (posedge clk or posedge reset)
begin
if(reset) begin
enable <= 0;
.........
end
else begin
case (state)
.......
enable <= some logic;
endcase
end
end
这样就没有错误信息。
可是如果写成
always @ (posedge clk or posedge reset)
begin
if(reset) begin
enable <= 0;
.........
end
else state <= next_state;
end
always @ (sensitivity list)
begin
case (state)
........
enable = some logic;
endcase
end
always @ (posedge clk or posedge reset)
begin
if(reset) begin
enable <= 0;
.........
end
else begin
case (state)
.......
enable <= some logic;
endcase
end
end
这样就没有错误信息。
可是如果写成
always @ (posedge clk or posedge reset)
begin
if(reset) begin
enable <= 0;
.........
end
else state <= next_state;
end
always @ (sensitivity list)
begin
case (state)
........
enable = some logic;
endcase
end