0.22uf is enough, you can even settle with smaller (0.1uF, 0.01uF), the key
problem here is how to get low ESL (parasitic inductance). component pins
have parasitic inductance, you need to minimize those parasitic inductance.
generally, the smaller the component size, the smaller the parasitic
inductance.
So in term of ground bounce minimizing,
0402 SMD > 0603 SMD >0805 SMD >1206 SMD >leaded caps.
5cm away from power pin is not close enough, but you can give it a try. If
you have commercial FPGA boards, you can take a look at how close they put
the bypassing caps.