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Can CADENCE simulate the temperature performance of a running chip
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Can CADENCE simulate the temperature performance of a running chip# EE - 电子工程
h*n
1
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S*a
2
会计Start Up
我和ld都是CPA, 尤其是ld, 在这行里呆了十几年了, 在KPMG 做了多年, 而我则在
PWC做过。我们精通税法,审计,公司财务,和 咨询等。有需要的可以和我们联系。
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a*e
3
We designed a mixed-signal ASIC and wants to find the hottest spot on the
chip so we could place a on-chip temp sensor next to it to monitor the peak
temp.
But how do we know which part of the ASIC is the hottest? Does CADENCE
simulate this? Is it gonna near the supply pad where the highest current
comes from the highest voltage or the digital section in which lots of
counting takes place?
Thanks.
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s*7
4
I don't think it should be near the supply pad since the voltage drop on it
is negligible thus drawing very small power. What you need to do is to
estimate the power of each block and place the sensor where the most power
is drawn.
In terms cadence, I'm not aware of any tool that simulates the on chip
temperature.
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C*Q
5
use totem

peak

【在 a******e 的大作中提到】
: We designed a mixed-signal ASIC and wants to find the hottest spot on the
: chip so we could place a on-chip temp sensor next to it to monitor the peak
: temp.
: But how do we know which part of the ASIC is the hottest? Does CADENCE
: simulate this? Is it gonna near the supply pad where the highest current
: comes from the highest voltage or the digital section in which lots of
: counting takes place?
: Thanks.

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f*3
6
不知道cadence SIP package可不可以仿这种情况?
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f*3
7
不知道cadence SIP package可不可以仿这种情况?
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