请问大家怎么买Contact Lens?# Fashion - 美丽时尚
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Apple（我所在的组）招 ASIC Engineer，最好有经验。如果感兴趣请发简历至
[email protected] 简历楼主会筛选
一下，如果没问题可以直接递给hiring manager。楼主直接参与招聘，会力挺国人。
如果是new grad，只需要名校＋high GPA，这样容易过简历关。
如果是有经验的在职跳槽，需要对coding micro architecture synthesis timing CDC
等等都有很好的理解
familiar with AXI protocol and design is a plus.
不需要太多的 data process knowledge but need to be excellent about control
flow and handshake
具体如下
Key Qualification:
RTL Logic Design experience of multi-million gate ASICs
Hands on experience in all aspects of the chip development process with
proficiency in front end tools and methodologies
Experience writing specifications and converting them to design
Experience with multiple clock domains and asynchronous interfaces
Experience or knowledge of system architecture, CPU & IP Integration, and
power and clock management designs is highly desirable
Ability to communicate effectively across all internal groups
Familiarity with software and operating concepts a plus
Familiarity with scripting languages like Perl or Tcl a plus
Job Description:
As an ASIC Design Engineer, you will have responsibilities spanning various
aspects of SOC design:
Write microarchitecture and/or design specifications
Design, implement, and debug complex logic designs
Integrate complex IPs into the SOC
Support all front end integration activities like Lint, CDC, Synthesis, and
ECO
Work with other engineers that are members of the SOC Design, SOC Design
Verification, Emulation, STA
公司常年招DV Engineer, General or Specific area 的都可以
[email protected] 简历楼主会筛选
一下，如果没问题可以直接递给hiring manager。楼主直接参与招聘，会力挺国人。
如果是new grad，只需要名校＋high GPA，这样容易过简历关。
如果是有经验的在职跳槽，需要对coding micro architecture synthesis timing CDC
等等都有很好的理解
familiar with AXI protocol and design is a plus.
不需要太多的 data process knowledge but need to be excellent about control
flow and handshake
具体如下
Key Qualification:
RTL Logic Design experience of multi-million gate ASICs
Hands on experience in all aspects of the chip development process with
proficiency in front end tools and methodologies
Experience writing specifications and converting them to design
Experience with multiple clock domains and asynchronous interfaces
Experience or knowledge of system architecture, CPU & IP Integration, and
power and clock management designs is highly desirable
Ability to communicate effectively across all internal groups
Familiarity with software and operating concepts a plus
Familiarity with scripting languages like Perl or Tcl a plus
Job Description:
As an ASIC Design Engineer, you will have responsibilities spanning various
aspects of SOC design:
Write microarchitecture and/or design specifications
Design, implement, and debug complex logic designs
Integrate complex IPs into the SOC
Support all front end integration activities like Lint, CDC, Synthesis, and
ECO
Work with other engineers that are members of the SOC Design, SOC Design
Verification, Emulation, STA
公司常年招DV Engineer, General or Specific area 的都可以
