Couple ASIC design and/or Verification engineer openings# JobHunting - 待字闺中
s*n
1 楼
1. In silicon valley
2. Skills requirement: verilog, system verilog, design compiler
3. Communication DSP background is a plus
4. Fresh MS or PhD is okey
Please respond with your resume if you are interested.
2. Skills requirement: verilog, system verilog, design compiler
3. Communication DSP background is a plus
4. Fresh MS or PhD is okey
Please respond with your resume if you are interested.