【工作机会】SERDES system architect in Silicon Valley# JobHunting - 待字闺中
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/* */。谢谢！
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We are a fast-growing IC design company located in Silicon Valley,
currently we have one opening for SERDES system architect; please send
your resume to [email protected]
/* */ if interested.
Job description: SERDES System Architect
- Architecture definition and verification for high-speed long-reach
SerDes interfaces (up to 56Gbps)
- Serial link modeling and link budget analysis to validate SerDes
system performance
- Adaptation algorithm design and specification development for Serdes
sub-block implementation
- Behavioral modeling at system level for critical circuit components
Requirements:
- MS or PhD with at least five years of experience in architecture
development for CDRs, TxFIR, linear equalizer, decision feedback
equalizer, and high-speed PLL
- Good knowledge of communication and signal processing theory with
working experience in one or more of the following areas: signal
modulation, error correction coding, noise/jitter analysis, signal
equalization/adaptation algorithms
- Good knowledge of signal-integrity issues and power optimization
tradeoff in architecture design fro high-speed SerDes
- Demonstrated proficiency in Matlab/Simulink, C++, and Verilog
- Experience in behavioral modeling for high-speed continuous-time and
discrete-time analog macros
- Familiarity with common SerDes protocols such as MIPI M-PHY,
USB1/2/3, PCIe1/2/3, SATA1/2/3, 10GKR, 16GFC, and CEI-28G from the
system architecture perspective is a strong plus
/* */。谢谢！
=====================================================================
We are a fast-growing IC design company located in Silicon Valley,
currently we have one opening for SERDES system architect; please send
your resume to [email protected]
/* */ if interested.
Job description: SERDES System Architect
- Architecture definition and verification for high-speed long-reach
SerDes interfaces (up to 56Gbps)
- Serial link modeling and link budget analysis to validate SerDes
system performance
- Adaptation algorithm design and specification development for Serdes
sub-block implementation
- Behavioral modeling at system level for critical circuit components
Requirements:
- MS or PhD with at least five years of experience in architecture
development for CDRs, TxFIR, linear equalizer, decision feedback
equalizer, and high-speed PLL
- Good knowledge of communication and signal processing theory with
working experience in one or more of the following areas: signal
modulation, error correction coding, noise/jitter analysis, signal
equalization/adaptation algorithms
- Good knowledge of signal-integrity issues and power optimization
tradeoff in architecture design fro high-speed SerDes
- Demonstrated proficiency in Matlab/Simulink, C++, and Verilog
- Experience in behavioral modeling for high-speed continuous-time and
discrete-time analog macros
- Familiarity with common SerDes protocols such as MIPI M-PHY,
USB1/2/3, PCIe1/2/3, SATA1/2/3, 10GKR, 16GFC, and CEI-28G from the
system architecture perspective is a strong plus