这个周末又去了灯具店,看到了新欢~~~# Living
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各位牛人哥哥姐姐大家好！
我是刚毕业的硕士，人在湾区，但不介意relocation,有过一年的美国大公司实习经验
，想找一下Digital ASIC的职位，Design， Verification，Validation，Application
我都愿意做，恳求各位牛人哥哥姐姐内推一下，不胜感激！
下面是我的skill set，请站内联系或邮件[email protected]
/* */
我知道不能白白让您帮忙，如果合适的话，事成之后我送您500～1000刀的礼物作为感
谢！
SKILL-SET
Specialties: ASIC Digital Design, Verilog (RTL) Coding, C/C++, PERL/TCL/
Python, SystemVerilog
STA: Timing model generation, Static Timing Analysis, Timing Closure, Power
and clock distribution, Set-up and Hold, Timing Fix
Backend design: Synthesis, SPICE model extraction, Floorplanning, Place and
route, CTS, RC delay extraction and correlation, Layout
Verification: Device and circuit simulation, Hardware validation, Test
structure development, self-checking test suites, Equivalence checking, DFT,
Block level Verification, Unit and System verification, Code coverage
analysis, Test bench development
Tools: Cadence, Synopsis, VCS, PrimeTime, Quartus, ModelSim,SPICE/HSPICE
我是刚毕业的硕士，人在湾区，但不介意relocation,有过一年的美国大公司实习经验
，想找一下Digital ASIC的职位，Design， Verification，Validation，Application
我都愿意做，恳求各位牛人哥哥姐姐内推一下，不胜感激！
下面是我的skill set，请站内联系或邮件[email protected]
/* */
我知道不能白白让您帮忙，如果合适的话，事成之后我送您500～1000刀的礼物作为感
谢！
SKILL-SET
Specialties: ASIC Digital Design, Verilog (RTL) Coding, C/C++, PERL/TCL/
Python, SystemVerilog
STA: Timing model generation, Static Timing Analysis, Timing Closure, Power
and clock distribution, Set-up and Hold, Timing Fix
Backend design: Synthesis, SPICE model extraction, Floorplanning, Place and
route, CTS, RC delay extraction and correlation, Layout
Verification: Device and circuit simulation, Hardware validation, Test
structure development, self-checking test suites, Equivalence checking, DFT,
Block level Verification, Unit and System verification, Code coverage
analysis, Test bench development
Tools: Cadence, Synopsis, VCS, PrimeTime, Quartus, ModelSim,SPICE/HSPICE
