Internal reference available for PHY verification engineer in San Diego# JobHunting - 待字闺中
r*9
1 楼
Requirements:
* MS/PHD degree in EE
* Verilog / System Verilog (OVM/UVM) / any scripting language
* 4+ years industry experience
* Mixed signal verification experience is a big plus
站内联系
Thanks
* MS/PHD degree in EE
* Verilog / System Verilog (OVM/UVM) / any scripting language
* 4+ years industry experience
* Mixed signal verification experience is a big plus
站内联系
Thanks