内推Principal IC Design Engineer (power team) (backend)# JobHunting - 待字闺中
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内推broadcom Infrastructure and Networking department ( 做基站和交换机芯
片）部门， 现在招 Principal IC Design Engineer，主要是在power team 做power
相关的工作， 有兴趣请发信致[email protected]
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下面是description
We are seeking a bright, self-motivated individual who is capable of
learning quickly on the job. This position will support RTL, verification,
physical design, circuit design and post-silicon teams to bring power
efficiency across the entire product design cycle. Responsibilities will
include full ownership of power estimation and reduction. The position will
require intelligent planning and a solid understanding of all aspects of
VLSI design. The role will have very high visibility on a complex, cutting
edge VLSI team operating in 28nm and 16nm process nodes.
Responsibilities include:
• Ownership of power distribution methodology and low power
implementation across multiple projects.
• Define low power methodology and run fullchip verification of power
grids.
• Develop methodology and tools for leakage recovery and power
reduction.
• Power gating-design/validation
• Multi VDD design
• Adaptive Voltage Scaling.
• On chip power management
• Run cycle accurate power simulations on RTL and gate views
• Drive front-end power reduction
• Post-silicon power validation
Job Requirements • Experience required is typically a BS degree and
15 years of experience, an MS degree 12 and years of experience or a PhD
and 9 years of experience or equivalent.
• BS (EE/Electrical Engineering) required, MS (EE ) preferred or
equivalent.
• Physical design expertise in state of the art ICs with emphasis on
VLSI physical design and methodology on 28nm and 16nm process nodes.
• Must have a proven track record of delivering tape-out quality GDSII
with silicon success
• Wide range of prior design experience including RTL, physical design
, digital and analog circuit design, chip finishing and silicon validation
• Experience with Place and Route, STA, Clock, Power and Noise
analysis.
• Strong hands on familiarity with Redhawk, Power Artist, VCS or
Incisive, Design Compiler, Calibre, Hspice, LEC, Formality, Primetime SI and
StarRC preferred.
• Proficiency using Perl, TCL.
• Must be able give technical presentations.
• Must be able to proactively drive and solve problems to
片）部门， 现在招 Principal IC Design Engineer，主要是在power team 做power
相关的工作， 有兴趣请发信致[email protected]
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/* ]]> */
下面是description
We are seeking a bright, self-motivated individual who is capable of
learning quickly on the job. This position will support RTL, verification,
physical design, circuit design and post-silicon teams to bring power
efficiency across the entire product design cycle. Responsibilities will
include full ownership of power estimation and reduction. The position will
require intelligent planning and a solid understanding of all aspects of
VLSI design. The role will have very high visibility on a complex, cutting
edge VLSI team operating in 28nm and 16nm process nodes.
Responsibilities include:
• Ownership of power distribution methodology and low power
implementation across multiple projects.
• Define low power methodology and run fullchip verification of power
grids.
• Develop methodology and tools for leakage recovery and power
reduction.
• Power gating-design/validation
• Multi VDD design
• Adaptive Voltage Scaling.
• On chip power management
• Run cycle accurate power simulations on RTL and gate views
• Drive front-end power reduction
• Post-silicon power validation
Job Requirements • Experience required is typically a BS degree and
15 years of experience, an MS degree 12 and years of experience or a PhD
and 9 years of experience or equivalent.
• BS (EE/Electrical Engineering) required, MS (EE ) preferred or
equivalent.
• Physical design expertise in state of the art ICs with emphasis on
VLSI physical design and methodology on 28nm and 16nm process nodes.
• Must have a proven track record of delivering tape-out quality GDSII
with silicon success
• Wide range of prior design experience including RTL, physical design
, digital and analog circuit design, chip finishing and silicon validation
• Experience with Place and Route, STA, Clock, Power and Noise
analysis.
• Strong hands on familiarity with Redhawk, Power Artist, VCS or
Incisive, Design Compiler, Calibre, Hspice, LEC, Formality, Primetime SI and
StarRC preferred.
• Proficiency using Perl, TCL.
• Must be able give technical presentations.
• Must be able to proactively drive and solve problems to