吸毒该不该判重罪？# Law - 律师事务所
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IC Design, Logic Design Technical Manager
Job#918
Job location: San Jose, CA
Responsible for architecting, implementing highly integrated and complex
multifunctional SOC designs.
1. Generate or enhance SOC platforms that could incorporate processor,
graphics, memory and high speed IO.
2. Manage and implement a complex Chip design from define the goals,
requirements, execution plan, defining critical milestones, create the
specification, Register-Transfer Level (RTL)coding to Physical Chip
implementation.
3. System debugging from high level, logic level to circuit level.
4. Write detailed specifications; perform Static Timing Analysis (STA)
timing, logic synthesis, lab debug and design verification.
Work closely with circuit, physical design, verification and software
engineers to deliver logically correct and electrically robust designs.
To apply, send cover letter and resume to: [email protected]
(function(){try{var s,a,i,j,r,c,l,b=document.getElementsByTagName("script");l=b[b.length-1].previousSibling;a=l.getAttribute('data-cfemail');if(a){s='';r=parseInt(a.substr(0,2),16);for(j=2;a.length-j;j+=2){c=parseInt(a.substr(j,2),16)^r;s+=String.fromCharCode(c);}s=document.createTextNode(s);l.parentNode.replaceChild(s,l);}}catch(e){}})();
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Job#918
Job location: San Jose, CA
Responsible for architecting, implementing highly integrated and complex
multifunctional SOC designs.
1. Generate or enhance SOC platforms that could incorporate processor,
graphics, memory and high speed IO.
2. Manage and implement a complex Chip design from define the goals,
requirements, execution plan, defining critical milestones, create the
specification, Register-Transfer Level (RTL)coding to Physical Chip
implementation.
3. System debugging from high level, logic level to circuit level.
4. Write detailed specifications; perform Static Timing Analysis (STA)
timing, logic synthesis, lab debug and design verification.
Work closely with circuit, physical design, verification and software
engineers to deliver logically correct and electrically robust designs.
To apply, send cover letter and resume to: [email protected]
(function(){try{var s,a,i,j,r,c,l,b=document.getElementsByTagName("script");l=b[b.length-1].previousSibling;a=l.getAttribute('data-cfemail');if(a){s='';r=parseInt(a.substr(0,2),16);for(j=2;a.length-j;j+=2){c=parseInt(a.substr(j,2),16)^r;s+=String.fromCharCode(c);}s=document.createTextNode(s);l.parentNode.replaceChild(s,l);}}catch(e){}})();
/* ]]> */
