求推荐300左右安卓手机# PDA - 掌中宝
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The successful candidate will join a highly talented, dynamic group of
engineers within Power Conversion Business Group to develop state of the art
AC/DC power control and solid state lighting control products. Individual
in this role is responsible for all aspect of digital physical design and
implementation from RTL to GDS design flow covering Place & Route and other
digital backend functions including synthesis, STA, DFT and LEC.
RESPONSIBILITIES:
. Lead the development of all aspects of the physical design flow from
netlist to GDS tape out including floor planning, place and route, clock
tree synthesis, timing closure and physical verification
. Work closely with front end designer to develop timing constraints and DFT
strategy, perform synthesis, ATPG and logic equivalent checking
. Drive physical design methodologies to achieve higher performance designs
and productivity enhancements through automation
. Work closely with analog and layout engineers on chip level floor plan and
integration.
. Conduct ECO flow for metal change re-spin
KNOWLEDGE, SKILLS:
. Minimum 8 years of experience with BSEE or 5 years of experience with MSEE
. Must have a proven track record of delivering tape-out quality GDSII with
silicon success
. Solid understanding of digital circuit design and Verilog.
. Solid understanding of digital design timing, physical synthesis and low
power design techniques.
. Power user of place and route tools such as ICC, Magma/Talus.
. Power user of Design Compiler, Primetime, Calibre.
. Experience with ASIC test methodologies including scan-insertion, ATPG and
logic BIST.
. Experience with logic equivalent checking and metal change ECO flow.
. Strong scripting skills with industry standard languages such as Perl,
Python and Tcl.
. Self-motivated and service-minded.
. Ability to work both independently and part of a team
. Excellent interpersonal, organizational and communications skills
Location: Campbell CA
站内信件联系
engineers within Power Conversion Business Group to develop state of the art
AC/DC power control and solid state lighting control products. Individual
in this role is responsible for all aspect of digital physical design and
implementation from RTL to GDS design flow covering Place & Route and other
digital backend functions including synthesis, STA, DFT and LEC.
RESPONSIBILITIES:
. Lead the development of all aspects of the physical design flow from
netlist to GDS tape out including floor planning, place and route, clock
tree synthesis, timing closure and physical verification
. Work closely with front end designer to develop timing constraints and DFT
strategy, perform synthesis, ATPG and logic equivalent checking
. Drive physical design methodologies to achieve higher performance designs
and productivity enhancements through automation
. Work closely with analog and layout engineers on chip level floor plan and
integration.
. Conduct ECO flow for metal change re-spin
KNOWLEDGE, SKILLS:
. Minimum 8 years of experience with BSEE or 5 years of experience with MSEE
. Must have a proven track record of delivering tape-out quality GDSII with
silicon success
. Solid understanding of digital circuit design and Verilog.
. Solid understanding of digital design timing, physical synthesis and low
power design techniques.
. Power user of place and route tools such as ICC, Magma/Talus.
. Power user of Design Compiler, Primetime, Calibre.
. Experience with ASIC test methodologies including scan-insertion, ATPG and
logic BIST.
. Experience with logic equivalent checking and metal change ECO flow.
. Strong scripting skills with industry standard languages such as Perl,
Python and Tcl.
. Self-motivated and service-minded.
. Ability to work both independently and part of a team
. Excellent interpersonal, organizational and communications skills
Location: Campbell CA
站内信件联系
