英国秋招 | Apple开放2024科技全职申请

• Minimum of BSc in EE.

• Experience with physical synthesis, including logic and PPA optimisation techniques.

• Understanding and application of physical design and static timing analysis principles.

• Proficient in Verilog and/or System Verilog and scripting languages.

- 关岗时间：招满即止，尽快申请

- 申请链接：https://sourl.cn/fMgXpe

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