b*y
2 楼
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randperm (昵称是什么？) 于 (Tue Sep 16 06:41:27 2008) 提到:
找单链表中的环，用两个指针，步长分别为1和2就行
问题是，为什么是1和2？其它步长行么？
看见讨论过，当时没仔细看，一下子想不明白了
大虾点拨一二？
谢了
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shime (虫) 于 (Tue Sep 16 10:02:45 2008) 提到:
我的想法是，其他步长也可以，只要它们不相等。但是选择1，2确实有好处。
1和2是最小的两个不一样的步长，所以相对其它的大步长可以省步数。
另外如果环的长度如果不能被步长差整除的话，大步长赶上小步长的时候多走的环数应
该就是步长差。所以在事先不知道环的长度的时候，步长差小一点也比较保险。
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thrust (WoW 无限期冬眠中) 于 (Tue Sep 16 12:48:53 2008)
randperm (昵称是什么？) 于 (Tue Sep 16 06:41:27 2008) 提到:
找单链表中的环，用两个指针，步长分别为1和2就行
问题是，为什么是1和2？其它步长行么？
看见讨论过，当时没仔细看，一下子想不明白了
大虾点拨一二？
谢了
☆─────────────────────────────────────☆
shime (虫) 于 (Tue Sep 16 10:02:45 2008) 提到:
我的想法是，其他步长也可以，只要它们不相等。但是选择1，2确实有好处。
1和2是最小的两个不一样的步长，所以相对其它的大步长可以省步数。
另外如果环的长度如果不能被步长差整除的话，大步长赶上小步长的时候多走的环数应
该就是步长差。所以在事先不知道环的长度的时候，步长差小一点也比较保险。
☆─────────────────────────────────────☆
thrust (WoW 无限期冬眠中) 于 (Tue Sep 16 12:48:53 2008)
l*o
3 楼
what is the difference between the two? Which library to link if I want to
compile MPI programs?
compile MPI programs?
n*l
4 楼
I'm making a 6-layer board and went through the DRC error report. There're
approximately 1000 error related to every single via I have on the board.
Can anyone who has experience with Allegro PCB software give me a hand?... I
spent the past several hours and couldn't find a fix for it.
The error is:
"Shape to Thru Via Spacing
Required spacing 8 MIL
Constraint set name DEFAULT
Etch subclass VD2"
I made the via myself in the PadStack.
Thanks a lot!!
approximately 1000 error related to every single via I have on the board.
Can anyone who has experience with Allegro PCB software give me a hand?... I
spent the past several hours and couldn't find a fix for it.
The error is:
"Shape to Thru Via Spacing
Required spacing 8 MIL
Constraint set name DEFAULT
Etch subclass VD2"
I made the via myself in the PadStack.
Thanks a lot!!
m*e
5 楼
you should start in August, and peak time is around November
c*l
6 楼
your vias are too dense???
re
I
【在 n*l 的大作中提到】
: I'm making a 6-layer board and went through the DRC error report. There're
: approximately 1000 error related to every single via I have on the board.
: Can anyone who has experience with Allegro PCB software give me a hand?... I
: spent the past several hours and couldn't find a fix for it.
: The error is:
: "Shape to Thru Via Spacing
: Required spacing 8 MIL
: Constraint set name DEFAULT
: Etch subclass VD2"
: I made the via myself in the PadStack.
re
I
【在 n*l 的大作中提到】
: I'm making a 6-layer board and went through the DRC error report. There're
: approximately 1000 error related to every single via I have on the board.
: Can anyone who has experience with Allegro PCB software give me a hand?... I
: spent the past several hours and couldn't find a fix for it.
: The error is:
: "Shape to Thru Via Spacing
: Required spacing 8 MIL
: Constraint set name DEFAULT
: Etch subclass VD2"
: I made the via myself in the PadStack.
c*6
7 楼
Is the VD2 the power layer?
You maybe need to check you flash shape in your via.
re
I
【在 n*l 的大作中提到】
: I'm making a 6-layer board and went through the DRC error report. There're
: approximately 1000 error related to every single via I have on the board.
: Can anyone who has experience with Allegro PCB software give me a hand?... I
: spent the past several hours and couldn't find a fix for it.
: The error is:
: "Shape to Thru Via Spacing
: Required spacing 8 MIL
: Constraint set name DEFAULT
: Etch subclass VD2"
: I made the via myself in the PadStack.
You maybe need to check you flash shape in your via.
re
I
【在 n*l 的大作中提到】
: I'm making a 6-layer board and went through the DRC error report. There're
: approximately 1000 error related to every single via I have on the board.
: Can anyone who has experience with Allegro PCB software give me a hand?... I
: spent the past several hours and couldn't find a fix for it.
: The error is:
: "Shape to Thru Via Spacing
: Required spacing 8 MIL
: Constraint set name DEFAULT
: Etch subclass VD2"
: I made the via myself in the PadStack.
n*l
8 楼
Yes VD2 is a power layer. I made VD2 a negative plane.
I'm not sure what is a flash shape?.. Just looked in the PadStack, didn't
find
flash shape option.
【在 c*********6 的大作中提到】
: Is the VD2 the power layer?
: You maybe need to check you flash shape in your via.
:
: re
: I
I'm not sure what is a flash shape?.. Just looked in the PadStack, didn't
find
flash shape option.
【在 c*********6 的大作中提到】
: Is the VD2 the power layer?
: You maybe need to check you flash shape in your via.
:
: re
: I
n*l
9 楼
There are some vias in the board are in the middle of nowhere, that is there
aren't any components within 75 mil of their vicinity, and those vias still
give me via-to-shape spacing error.
En, I set the constraint in Setup -> Constraint -> Physical (lines/vias)
rule set : Set Values ..
aren't any components within 75 mil of their vicinity, and those vias still
give me via-to-shape spacing error.
En, I set the constraint in Setup -> Constraint -> Physical (lines/vias)
rule set : Set Values ..
c*6
10 楼
Flash shape in pad will decide how to connect or isolate the via to internal
layers like GND or POWER.
Normally you gotta design the flash before designing the pad or via.
【在 n*l 的大作中提到】
: Yes VD2 is a power layer. I made VD2 a negative plane.
: I'm not sure what is a flash shape?.. Just looked in the PadStack, didn't
: find
: flash shape option.
layers like GND or POWER.
Normally you gotta design the flash before designing the pad or via.
【在 n*l 的大作中提到】
: Yes VD2 is a power layer. I made VD2 a negative plane.
: I'm not sure what is a flash shape?.. Just looked in the PadStack, didn't
: find
: flash shape option.
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