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贡献几道RING OSC相关的面试题
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贡献几道RING OSC相关的面试题# EE - 电子工程
s*n
1
我刚才上网查了一下机票,八月底走,九月回的,就没有超过一千块钱的机票
avatar
b*1
2
多年从事产妇护理及新生儿照顾,经验丰富。擅长台式月子餐,有体检报告。位于
Maryland,大华府地区,也可飞外州。有照顾双胞胎经验,有意者可wx、站内联系。
wx: xy2331030908
avatar
s*8
3
RT,或者是购买也可以,老是在那个网上买不到。6到8分钟就可以,站内联系,谢谢!
avatar
p*r
4
要剧情有剧情,要色情暴力有色情暴力。
比起BB,差就差在海森伯格色绝望感和新墨西哥的沧桑感。评分8.6很实在。
avatar
C*l
5
本地秋色,齁着没有?(右键点击view image看大图)
1
2
3
4
5
6
7
8
9
10
avatar
a*u
6
☆─────────────────────────────────────☆
pattern (放手 ) 于 (Sat Jan 24 13:19:02 2009) 提到:
杂阿含中有两千多处讲到”苦” 近300处说”厌离”
runsun waichi 两大有名id都不表赞成
可学而不思(修)则罔 思(修)而不学则殆
虽然有死读书的嫌疑 我还是把一部分经文po一下 以昭公信
佛法中何谓”正观”?
大正藏杂阿含 第1经
如是我闻
一时。佛住舍卫国祇树给孤独园
尔时。世尊告诸比丘。当观色无常。如是观者。则为正观。正观者。则生厌离。
厌离者。喜贪尽。喜贪尽者。说心解脱
如是观受.想.行.识无常。如是观者。则为正观。正观者。则生厌离。厌离者
。喜贪尽。喜贪尽者。说心解脱
如是。比丘。心解脱者。若欲自证。则能自证。我生已尽。梵行已立。所作已作
。自知不受后有。如观无常。苦.空.非我亦复如是
时。诸比丘闻佛所说。欢喜奉行
大正藏杂阿含 第9经
如是我闻
一时。佛住舍卫国祇树给孤独园
尔时。世尊告诸比丘。色无常。无常即苦。苦即非我。非我者亦非我所。如是观
者。
avatar
x*g
7
1. Draw the connection with 3 single-ended inverters in series. Can you do
with 2 inverters? Why? Draw the differential version.
2. How to size PMOS transistor sizes relative to NMOS to get the symmetric
rising/falling edges? Why we want to do this?
3. Now if we increase all the transistors’ sizes by 10X, what will be the
new oscillation freq ?
4. Typical ring oscillator duty cycle variation range across PVT?
Which one of the PVT variations affects the most? Methods to adjust
the duty cycle close to 50%?
大家没事玩玩.
avatar
v*i
8
如果都是8月底放暑假,你觉得那个时候的机票还会便宜?
avatar
b*1
9
顶贴~
avatar
l*y
10
我还以为就我买不到卡。那个网站到底怎么回事啊?

【在 s**********8 的大作中提到】
: RT,或者是购买也可以,老是在那个网上买不到。6到8分钟就可以,站内联系,谢谢!
avatar
s*u
11
wait for the solutions. BTW, for Q3, increase the sizes by 10X, you mean
aspect ratio W/L increased by 10x, or both W x10, and L x 10?
avatar
b*1
12
avatar
y*e
13
等LZ来贴答案。。1懂半个,2、3貌似懂,4完全不懂。。。菜鸟飘过。。。
avatar
b*1
14
avatar
a*y
15
1 3 stages 很简单,直接feedback。 even级的osc是可能的,但是两级的是不可能的
。考虑phase delay from the first pole (dominated),一级的最大相移是90°,理
想情况下,所以整个为180°。又是正feedback,自己看满足osc震荡的两个条件么?差
分结构?我不太懂,是说tank结构的osc么?ring怎么会有差分?
2 一般来说p是n的两倍,因为mobility of the channel 电子和空穴。但实际电路在1.
4到1.6左右。Tplh=Tphl是一个理想的翻转过程,这样的square wave的distortion and
glitch最小,频率的一次的谐波占到最大比重。(就是频率特性)
3增到10x的width的话,如果不考虑阈值和工艺的变化的话,应该是delay会增大10倍,
频率会减小10x
4 10%左右。(0.18的工艺来说,这个问题,问的是typical,这个好傻,typical是随
着工艺变化而变化的,是95n?。18?。35?到底是哪个?)voltage。改变电压,不能
话,改变size。

【在 x***g 的大作中提到】
: 1. Draw the connection with 3 single-ended inverters in series. Can you do
: with 2 inverters? Why? Draw the differential version.
: 2. How to size PMOS transistor sizes relative to NMOS to get the symmetric
: rising/falling edges? Why we want to do this?
: 3. Now if we increase all the transistors’ sizes by 10X, what will be the
: new oscillation freq ?
: 4. Typical ring oscillator duty cycle variation range across PVT?
: Which one of the PVT variations affects the most? Methods to adjust
: the duty cycle close to 50%?
: 大家没事玩玩.

avatar
b*1
16
顶贴~
avatar
s*u
17
1. Barkhausen's criterion. Differential ring oscillator is very widely used,
Maneatis' PLL paper provides very good implementation. There are tons of
papers about diff ring osc.
2. One of the reason about symmetry is for jitter/phase noise improvement.
Hajimiri's paper describes it pretty clearly. Don't know if there's other
considerations.
3. It doesn't change from theory if Wx10, L remains. delay will not change
because current also increases by 10 times.
4. Don't know... waiting for solutions.

1.
and

【在 a**********y 的大作中提到】
: 1 3 stages 很简单,直接feedback。 even级的osc是可能的,但是两级的是不可能的
: 。考虑phase delay from the first pole (dominated),一级的最大相移是90°,理
: 想情况下,所以整个为180°。又是正feedback,自己看满足osc震荡的两个条件么?差
: 分结构?我不太懂,是说tank结构的osc么?ring怎么会有差分?
: 2 一般来说p是n的两倍,因为mobility of the channel 电子和空穴。但实际电路在1.
: 4到1.6左右。Tplh=Tphl是一个理想的翻转过程,这样的square wave的distortion and
: glitch最小,频率的一次的谐波占到最大比重。(就是频率特性)
: 3增到10x的width的话,如果不考虑阈值和工艺的变化的话,应该是delay会增大10倍,
: 频率会减小10x
: 4 10%左右。(0.18的工艺来说,这个问题,问的是typical,这个好傻,typical是随

avatar
b*1
18
多年从事产妇护理及新生儿照顾,经验丰富。擅长台式月子餐,有体检报告。位于
Maryland,大华府地区,也可飞外州。有照顾双胞胎经验,有意者可wx、站内联系。
wx: xy2331030908
avatar
x*g
19
喔, 既然有人有兴趣, 那我就先扔个三瓜两枣. 很显然, 有些问题不是三言两语
讲得清的, 有些问题是OPEN的.
首先申明, 这些是实战题, 可不是我拍脑瓜现摆弄. 但妙在它们出自一个DIGITAL GUY
之口, 就让我觉得有点小意思了.

used,
Note 2 single-ended inverters in series will be a latch.
One hint: duty cycle.
The answer is correct if neglecting wire parasitic cap. And the
assumption here is of course, Lmin stays the same and W is increased
by 10X to get 10X stronger. But the best way to understand is to
think about the freq dependence on the RC product.
This is a very open question and can go as deep as how much your
circuit knowledge can go. I knew at least 3 possible solutions.
I can share more later when I have more time.

【在 s******u 的大作中提到】
: 1. Barkhausen's criterion. Differential ring oscillator is very widely used,
: Maneatis' PLL paper provides very good implementation. There are tons of
: papers about diff ring osc.
: 2. One of the reason about symmetry is for jitter/phase noise improvement.
: Hajimiri's paper describes it pretty clearly. Don't know if there's other
: considerations.
: 3. It doesn't change from theory if Wx10, L remains. delay will not change
: because current also increases by 10 times.
: 4. Don't know... waiting for solutions.
:

avatar
b*1
20
顶贴~
avatar
v*a
21
调查下关心这些问题的都是什么背景的呢
电路设计还是半导体工艺?
我是搞半导体工艺方面的,RO本来不是很懂,但是现在接触的很多,
RO在工艺中是一个 process monitor,不知道在实际电路中啥作用呢
avatar
b*1
22
avatar
v*a
23
貌似2楼和我差不多,1,4不懂,2,3还行,
2, tpd=Ceff*Vdd*(1/Ieff,n*Wn/Ln +1/Ieff,p*Wp/Lp )
想symmetric 的话就需要后两项相等,而Ieff=Ieff(Vth,Cox,u)等诸多因素的影响,不
单单是mobility,综合的效果就是Wp大概是Lp的1.5倍左右。
3, 如上,如果W, L同时增大10倍的话,主要的变化来自Vth,一般来说Vth对于W的变
化不大(当然也看具体工艺),而NCE引起的Vth roll over不是一个简单的单调函数,
pfet 和 nfet 也是不一样的,工艺不同,器件不同,变化也是不同,所以只能说,f怎
么变不可知。
大家认为呢
avatar
b*1
24
avatar
w*n
25
1. Draw the connection with 3 single-ended inverters in series. Can you do
with 2 inverters? Why? Draw the differential version.
-2 single ended inverters cannot oscillate, differential version can, take 2
-stage differential as 4-stage single ended;
2. How to size PMOS transistor sizes relative to NMOS to get the symmetric
rising/falling edges? Why we want to do this?
-Symmetric rising/falling edge can achieve better flicker noise, refer to
Hajimiri noise model;
3. Now if we increase all the transistors’ sizes by 10X, what will be the
new oscillation freq ?
-Roughly the same; freq=I/C=10*I/10*C
4. Typical ring oscillator duty cycle variation range across PVT?
Which one of the PVT variations affects the most? Methods to adjust
the duty cycle close to 50%?
-ac coupling
avatar
b*1
26
顶贴,长期有效
avatar
x*g
27
1. Draw the connection with 3 single-ended inverters in series. Can you do
with 2 inverters? Why? Draw the differential version.
2. How to size PMOS transistor sizes relative to NMOS to get the symmetric
rising/falling edges? Why we want to do this?
3. Now if we increase all the transistors’ sizes by 10X, what will be the
new oscillation freq ?
4. Typical ring oscillator duty cycle variation range across PVT?
Which one of the PVT variations affects the most? Methods to adjust
the duty cycle close to 50%?
大家没事玩玩.
avatar
b*1
28
顶贴,长期有效
avatar
s*u
29
wait for the solutions. BTW, for Q3, increase the sizes by 10X, you mean
aspect ratio W/L increased by 10x, or both W x10, and L x 10?
avatar
b*1
30
顶贴,长期有效
avatar
y*e
31
等LZ来贴答案。。1懂半个,2、3貌似懂,4完全不懂。。。菜鸟飘过。。。
avatar
b*1
32
顶贴,长期有效
avatar
a*y
33
1 3 stages 很简单,直接feedback。 even级的osc是可能的,但是两级的是不可能的
。考虑phase delay from the first pole (dominated),一级的最大相移是90°,理
想情况下,所以整个为180°。又是正feedback,自己看满足osc震荡的两个条件么?差
分结构?我不太懂,是说tank结构的osc么?ring怎么会有差分?
2 一般来说p是n的两倍,因为mobility of the channel 电子和空穴。但实际电路在1.
4到1.6左右。Tplh=Tphl是一个理想的翻转过程,这样的square wave的distortion and
glitch最小,频率的一次的谐波占到最大比重。(就是频率特性)
3增到10x的width的话,如果不考虑阈值和工艺的变化的话,应该是delay会增大10倍,
频率会减小10x
4 10%左右。(0.18的工艺来说,这个问题,问的是typical,这个好傻,typical是随
着工艺变化而变化的,是95n?。18?。35?到底是哪个?)voltage。改变电压,不能
话,改变size。

【在 x***g 的大作中提到】
: 1. Draw the connection with 3 single-ended inverters in series. Can you do
: with 2 inverters? Why? Draw the differential version.
: 2. How to size PMOS transistor sizes relative to NMOS to get the symmetric
: rising/falling edges? Why we want to do this?
: 3. Now if we increase all the transistors’ sizes by 10X, what will be the
: new oscillation freq ?
: 4. Typical ring oscillator duty cycle variation range across PVT?
: Which one of the PVT variations affects the most? Methods to adjust
: the duty cycle close to 50%?
: 大家没事玩玩.

avatar
b*1
34
顶贴,长期有效
avatar
s*u
35
1. Barkhausen's criterion. Differential ring oscillator is very widely used,
Maneatis' PLL paper provides very good implementation. There are tons of
papers about diff ring osc.
2. One of the reason about symmetry is for jitter/phase noise improvement.
Hajimiri's paper describes it pretty clearly. Don't know if there's other
considerations.
3. It doesn't change from theory if Wx10, L remains. delay will not change
because current also increases by 10 times.
4. Don't know... waiting for solutions.

1.
and

【在 a**********y 的大作中提到】
: 1 3 stages 很简单,直接feedback。 even级的osc是可能的,但是两级的是不可能的
: 。考虑phase delay from the first pole (dominated),一级的最大相移是90°,理
: 想情况下,所以整个为180°。又是正feedback,自己看满足osc震荡的两个条件么?差
: 分结构?我不太懂,是说tank结构的osc么?ring怎么会有差分?
: 2 一般来说p是n的两倍,因为mobility of the channel 电子和空穴。但实际电路在1.
: 4到1.6左右。Tplh=Tphl是一个理想的翻转过程,这样的square wave的distortion and
: glitch最小,频率的一次的谐波占到最大比重。(就是频率特性)
: 3增到10x的width的话,如果不考虑阈值和工艺的变化的话,应该是delay会增大10倍,
: 频率会减小10x
: 4 10%左右。(0.18的工艺来说,这个问题,问的是typical,这个好傻,typical是随

avatar
b*1
36
顶贴,长期有效
avatar
x*g
37
喔, 既然有人有兴趣, 那我就先扔个三瓜两枣. 很显然, 有些问题不是三言两语
讲得清的, 有些问题是OPEN的.
首先申明, 这些是实战题, 可不是我拍脑瓜现摆弄. 但妙在它们出自一个DIGITAL GUY
之口, 就让我觉得有点小意思了.

used,
Note 2 single-ended inverters in series will be a latch.
One hint: duty cycle.
The answer is correct if neglecting wire parasitic cap. And the
assumption here is of course, Lmin stays the same and W is increased
by 10X to get 10X stronger. But the best way to understand is to
think about the freq dependence on the RC product.
This is a very open question and can go as deep as how much your
circuit knowledge can go. I knew at least 3 possible solutions.
I can share more later when I have more time.

【在 s******u 的大作中提到】
: 1. Barkhausen's criterion. Differential ring oscillator is very widely used,
: Maneatis' PLL paper provides very good implementation. There are tons of
: papers about diff ring osc.
: 2. One of the reason about symmetry is for jitter/phase noise improvement.
: Hajimiri's paper describes it pretty clearly. Don't know if there's other
: considerations.
: 3. It doesn't change from theory if Wx10, L remains. delay will not change
: because current also increases by 10 times.
: 4. Don't know... waiting for solutions.
:

avatar
d*l
38
请问您还在从事家政或是月嫂行业吗?我们想邀请您加入我们的家政人才库。我们会帮
助您接触到更多的雇主,获得工作机会。平台使用免费。不收佣金。可以直接添加我们
的微信ayiconnection咨询详细情况。
avatar
v*a
39
调查下关心这些问题的都是什么背景的呢
电路设计还是半导体工艺?
我是搞半导体工艺方面的,RO本来不是很懂,但是现在接触的很多,
RO在工艺中是一个 process monitor,不知道在实际电路中啥作用呢
avatar
b*1
40
顶贴,长期有效。
avatar
v*a
41
貌似2楼和我差不多,1,4不懂,2,3还行,
2, tpd=Ceff*Vdd*(1/Ieff,n*Wn/Ln +1/Ieff,p*Wp/Lp )
想symmetric 的话就需要后两项相等,而Ieff=Ieff(Vth,Cox,u)等诸多因素的影响,不
单单是mobility,综合的效果就是Wp大概是Lp的1.5倍左右。
3, 如上,如果W, L同时增大10倍的话,主要的变化来自Vth,一般来说Vth对于W的变
化不大(当然也看具体工艺),而NCE引起的Vth roll over不是一个简单的单调函数,
pfet 和 nfet 也是不一样的,工艺不同,器件不同,变化也是不同,所以只能说,f怎
么变不可知。
大家认为呢
avatar
b*1
42
顶贴,长期有效
avatar
w*n
43
1. Draw the connection with 3 single-ended inverters in series. Can you do
with 2 inverters? Why? Draw the differential version.
-2 single ended inverters cannot oscillate, differential version can, take 2
-stage differential as 4-stage single ended;
2. How to size PMOS transistor sizes relative to NMOS to get the symmetric
rising/falling edges? Why we want to do this?
-Symmetric rising/falling edge can achieve better flicker noise, refer to
Hajimiri noise model;
3. Now if we increase all the transistors’ sizes by 10X, what will be the
new oscillation freq ?
-Roughly the same; freq=I/C=10*I/10*C
4. Typical ring oscillator duty cycle variation range across PVT?
Which one of the PVT variations affects the most? Methods to adjust
the duty cycle close to 50%?
-ac coupling
avatar
d*l
44
请问您还在从事家政或是月嫂行业吗?我们想邀请您加入我们的家政人才库。我们会帮
助您接触到更多的雇主,获得工作机会。平台使用免费。不收佣金。可以直接添加我们
的微信ayiconnection咨询详细情况。
avatar
y*e
45
大家分歧好大的样子,单就第3个,也貌似是最简单的一个来讲,答案是不是,只增加W
,f几乎不变; 如果W 和L都增加,我怎么算着是100倍的降低呢,哪里错了?
我的思路:
时间常数t=RC, R 与W/L成反比,C于W*L成正比,那RC应该是与L^2成正比喽?
avatar
b*1
46
顶贴,长期有效。
avatar
j*e
47
1 中的differential应该指的是用差分放大器
4 确定只有10%? 我印象中经常有30%,可以加个D触发器也能产生50%

1.
and

【在 a**********y 的大作中提到】
: 1 3 stages 很简单,直接feedback。 even级的osc是可能的,但是两级的是不可能的
: 。考虑phase delay from the first pole (dominated),一级的最大相移是90°,理
: 想情况下,所以整个为180°。又是正feedback,自己看满足osc震荡的两个条件么?差
: 分结构?我不太懂,是说tank结构的osc么?ring怎么会有差分?
: 2 一般来说p是n的两倍,因为mobility of the channel 电子和空穴。但实际电路在1.
: 4到1.6左右。Tplh=Tphl是一个理想的翻转过程,这样的square wave的distortion and
: glitch最小,频率的一次的谐波占到最大比重。(就是频率特性)
: 3增到10x的width的话,如果不考虑阈值和工艺的变化的话,应该是delay会增大10倍,
: 频率会减小10x
: 4 10%左右。(0.18的工艺来说,这个问题,问的是typical,这个好傻,typical是随

avatar
b*1
48
顶贴,长期有效。
avatar
j*e
49
基本都是基础吧,razavi的那章基本都囊括了
avatar
b*1
50
顶贴,长期有效。
avatar
j*e
51
1.5倍可不一定。。。 很多要2-3倍才可以

【在 v********a 的大作中提到】
: 貌似2楼和我差不多,1,4不懂,2,3还行,
: 2, tpd=Ceff*Vdd*(1/Ieff,n*Wn/Ln +1/Ieff,p*Wp/Lp )
: 想symmetric 的话就需要后两项相等,而Ieff=Ieff(Vth,Cox,u)等诸多因素的影响,不
: 单单是mobility,综合的效果就是Wp大概是Lp的1.5倍左右。
: 3, 如上,如果W, L同时增大10倍的话,主要的变化来自Vth,一般来说Vth对于W的变
: 化不大(当然也看具体工艺),而NCE引起的Vth roll over不是一个简单的单调函数,
: pfet 和 nfet 也是不一样的,工艺不同,器件不同,变化也是不同,所以只能说,f怎
: 么变不可知。
: 大家认为呢

avatar
j*e
52
正确

加W

【在 y*****e 的大作中提到】
: 大家分歧好大的样子,单就第3个,也貌似是最简单的一个来讲,答案是不是,只增加W
: ,f几乎不变; 如果W 和L都增加,我怎么算着是100倍的降低呢,哪里错了?
: 我的思路:
: 时间常数t=RC, R 与W/L成反比,C于W*L成正比,那RC应该是与L^2成正比喽?

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