Thank you for sharing.Your discussion is very informing.
I'd like to make a few comments:
1. is MP0 a JFET? If so, the device symbol you drew is incorrect.
2. Almost all band gap start up ckt can be properly simulated. That is, you
shall be able to predict if the ckt could latch up to off-condition. Keep in
mind start up problem is essentially a DC operating point problem, not a
transient issue.I guess you either use transient sim or power supply DC
sweep to verify your design, which is not the right way to do it.
3. In the first schematic, the start up ckt Q2 injects current into base of
Q1/Q0 as well as external load current on VBG (not shown in the schematic).
This could be a little less efficient. What if adding one nmos diode in
series with Q3/Q4, increase Q2 based by one nmos diode voltage drop, connect
Q2 emitter to MN3 gate? By doing so, you can prevent Q1 from saturation.
4. In the second schematic, it's interesting to see how you employ a current
comparator (normal bandgap current vs JFET current) to toggle the start up
ckt. I wonder if it could introduce new latch up condition - although as you
describe, it's not observed in the test.
5. ContinentQQ's comment sounds right to me.
'btw, 如果没有MN1/2/3和MP3，这个电路好像还是能工作？'
He meant connecting Q1 base to Q1 collector here.
Certainly the simplified bandgap ckt can't take any dc load current.
Above devices are not part of the start up ckt in the first schematic.
I was considering writing a paper on start up ckt in general.
I might come up some short version first for my fellow Chinese engineers
here.
Again thank you for sharing. Happy holiday!
