人生若只如初见# Love - 情爱幽幽
f*r
1 楼
今天manager突然说可以找fresh grad. 如果觉得fit的话, 跟我联系
This position requires an understanding of RTL to GDS flows, CMOS device
operation and advanced layout rules.
Responsibilities:
Ownership of design floor planning, synthesis, DFT, place and route,
clock and power distribution, static timing analysis, signal integrity
analysis, physical verification.
Use circuit design skills to verify clock and power implementation.
Contribute to developing physical design methodologies and RTL to GDS
flow automation.
Requirements:
BSEE, MSEE Preferred
7+ years directly related physical design expertise in state of the art
ICs with emphasis on VLSI physical design and methodology on 90, 65 or
45 nanometer process nodes.
A solid understanding of digital circuit design and Verilog.
Basic understanding for circuit design of custom macro blocks such as
RAMs, Register Files, CAMs, high-speed IO drivers and other IP cells.
Power user of place and route tools such as Atoptech, ICC, Magma or
Cadence SOCe
Able to identify, extract and simulate critical paths using Hspice.
Able to create schematics from RTL for semi-custom designs.
Strong hands on familiarity with Design Compiler, Calibre, Hspice, LEC,
Formality, Primetime SI, Redhawk and StarRC preferred.
Proficiency using Perl, TCL.
Able to work in a small team environment.
Must have a proven track record of delivering tape-out quality GDSII
with silicon success.
This position requires an understanding of RTL to GDS flows, CMOS device
operation and advanced layout rules.
Responsibilities:
Ownership of design floor planning, synthesis, DFT, place and route,
clock and power distribution, static timing analysis, signal integrity
analysis, physical verification.
Use circuit design skills to verify clock and power implementation.
Contribute to developing physical design methodologies and RTL to GDS
flow automation.
Requirements:
BSEE, MSEE Preferred
7+ years directly related physical design expertise in state of the art
ICs with emphasis on VLSI physical design and methodology on 90, 65 or
45 nanometer process nodes.
A solid understanding of digital circuit design and Verilog.
Basic understanding for circuit design of custom macro blocks such as
RAMs, Register Files, CAMs, high-speed IO drivers and other IP cells.
Power user of place and route tools such as Atoptech, ICC, Magma or
Cadence SOCe
Able to identify, extract and simulate critical paths using Hspice.
Able to create schematics from RTL for semi-custom designs.
Strong hands on familiarity with Design Compiler, Calibre, Hspice, LEC,
Formality, Primetime SI, Redhawk and StarRC preferred.
Proficiency using Perl, TCL.
Able to work in a small team environment.
Must have a proven track record of delivering tape-out quality GDSII
with silicon success.
