A*J
2 楼
81k base + 3k share ($28 per share) + bonus
fresh ms. (with 3 yrs work exp in China)
Company market value 8 billion.
Still waiting for another company with its market value 16 billion (
fortune 500)
what's my next step? Thank you. Do I still need to wait for 16b company. I
know I may still have chance to get into.
fresh ms. (with 3 yrs work exp in China)
Company market value 8 billion.
Still waiting for another company with its market value 16 billion (
fortune 500)
what's my next step? Thank you. Do I still need to wait for 16b company. I
know I may still have chance to get into.
G*h
3 楼
明年有好戏看了
28nm 的, 比 arm 工艺牛
速度, 耗电量不知道如何
28nm 的, 比 arm 工艺牛
速度, 耗电量不知道如何
a*9
4 楼
要高升了吧, 过几天在MIT的主页上就看到老李了...
c*p
5 楼
Good one.
我来查查我公司的 market value.
我来查查我公司的 market value.
k*n
8 楼
bso阿。。。
【在 A***J 的大作中提到】
: 81k base + 3k share ($28 per share) + bonus
: fresh ms. (with 3 yrs work exp in China)
: Company market value 8 billion.
: Still waiting for another company with its market value 16 billion (
: fortune 500)
: what's my next step? Thank you. Do I still need to wait for 16b company. I
: know I may still have chance to get into.
【在 A***J 的大作中提到】
: 81k base + 3k share ($28 per share) + bonus
: fresh ms. (with 3 yrs work exp in China)
: Company market value 8 billion.
: Still waiting for another company with its market value 16 billion (
: fortune 500)
: what's my next step? Thank you. Do I still need to wait for 16b company. I
: know I may still have chance to get into.
G*h
9 楼
天下大乱。。。
不过 Intel 版权费肯定比 arm 高
适合果子使用
不过 Intel 版权费肯定比 arm 高
适合果子使用
s*f
11 楼
location?
A*J
14 楼
bay area
s*e
16 楼
老李的确是失踪了。大家可以静静等待老李的好消息。我在这里就不剧透了。
p*2
17 楼
啥major啊?
【在 A***J 的大作中提到】
: 81k base + 3k share ($28 per share) + bonus
: fresh ms. (with 3 yrs work exp in China)
: Company market value 8 billion.
: Still waiting for another company with its market value 16 billion (
: fortune 500)
: what's my next step? Thank you. Do I still need to wait for 16b company. I
: know I may still have chance to get into.
【在 A***J 的大作中提到】
: 81k base + 3k share ($28 per share) + bonus
: fresh ms. (with 3 yrs work exp in China)
: Company market value 8 billion.
: Still waiting for another company with its market value 16 billion (
: fortune 500)
: what's my next step? Thank you. Do I still need to wait for 16b company. I
: know I may still have chance to get into.
p*r
18 楼
ARM already has got all market share and the ecosystem.
It's hard for INTEL to get some market share without pricing
the chip aggressively. INTEL business model is high price and
high margin. It will have to lose money in order to get some
market share. I doubt if INTEL can continue doing it in 2-3
years. At the end INTEL may quit the game by itself due
to the touch competition. INTEL could use the same fab to make
high margin product, why bother to make a $5-$20 chip to compete.
TI $5/chip will kill a lot of the small players who used to be
in those media player market, semi smart phones.
【在 G*****h 的大作中提到】
: 编译还不就是分把钟而已
: 就是芯片贵啊,不可能跟 NV 一样 $25,TI $5
It's hard for INTEL to get some market share without pricing
the chip aggressively. INTEL business model is high price and
high margin. It will have to lose money in order to get some
market share. I doubt if INTEL can continue doing it in 2-3
years. At the end INTEL may quit the game by itself due
to the touch competition. INTEL could use the same fab to make
high margin product, why bother to make a $5-$20 chip to compete.
TI $5/chip will kill a lot of the small players who used to be
in those media player market, semi smart phones.
【在 G*****h 的大作中提到】
: 编译还不就是分把钟而已
: 就是芯片贵啊,不可能跟 NV 一样 $25,TI $5
A*J
20 楼
CompE
h*k
23 楼
你可以用这个offer去催一下你等的公司,应该很快就有消息给不给你offer了。
【在 A***J 的大作中提到】
: 81k base + 3k share ($28 per share) + bonus
: fresh ms. (with 3 yrs work exp in China)
: Company market value 8 billion.
: Still waiting for another company with its market value 16 billion (
: fortune 500)
: what's my next step? Thank you. Do I still need to wait for 16b company. I
: know I may still have chance to get into.
【在 A***J 的大作中提到】
: 81k base + 3k share ($28 per share) + bonus
: fresh ms. (with 3 yrs work exp in China)
: Company market value 8 billion.
: Still waiting for another company with its market value 16 billion (
: fortune 500)
: what's my next step? Thank you. Do I still need to wait for 16b company. I
: know I may still have chance to get into.
s*3
28 楼
怎么都在做板子、手机,不已经够多了么,不敢再来个什么创新的东西么
a*k
29 楼
闭关练绝技去了。过几天来亮瞎大家的眼
g*g
30 楼
这个东西就是耗电和性能,如果intel能两者都比arm强,还比arm
便宜,自然很有的做,但x86的架构先天不足,不是太容易。
【在 p*********r 的大作中提到】
: ARM already has got all market share and the ecosystem.
: It's hard for INTEL to get some market share without pricing
: the chip aggressively. INTEL business model is high price and
: high margin. It will have to lose money in order to get some
: market share. I doubt if INTEL can continue doing it in 2-3
: years. At the end INTEL may quit the game by itself due
: to the touch competition. INTEL could use the same fab to make
: high margin product, why bother to make a $5-$20 chip to compete.
: TI $5/chip will kill a lot of the small players who used to be
: in those media player market, semi smart phones.
便宜,自然很有的做,但x86的架构先天不足,不是太容易。
【在 p*********r 的大作中提到】
: ARM already has got all market share and the ecosystem.
: It's hard for INTEL to get some market share without pricing
: the chip aggressively. INTEL business model is high price and
: high margin. It will have to lose money in order to get some
: market share. I doubt if INTEL can continue doing it in 2-3
: years. At the end INTEL may quit the game by itself due
: to the touch competition. INTEL could use the same fab to make
: high margin product, why bother to make a $5-$20 chip to compete.
: TI $5/chip will kill a lot of the small players who used to be
: in those media player market, semi smart phones.
s*v
42 楼
干,intel出的什么玩意啊?idle 2.6w!! full function 3.6w. vs. tegra 3 <2w
under full load. idle的时候比别人工作还要费电!
Unfortunately, things aren't as rosy on the power consumption front, as
Medfield is allegedly consuming an estimated 2.6 watts when idle, and 3.6
watts when weighed down by a 720p Flash video
http://www.theverge.com/2011/12/27/2664454/intel-medfield-table
under full load. idle的时候比别人工作还要费电!
Unfortunately, things aren't as rosy on the power consumption front, as
Medfield is allegedly consuming an estimated 2.6 watts when idle, and 3.6
watts when weighed down by a 720p Flash video
http://www.theverge.com/2011/12/27/2664454/intel-medfield-table
s*v
44 楼
蚂蚁同学,能不能从科学的角度解释一下,为啥intel x86耗电这么高啊,这样的话,
是不是只能等tri-gate 20nm了?
【在 s******v 的大作中提到】
: 干,intel出的什么玩意啊?idle 2.6w!! full function 3.6w. vs. tegra 3 <2w
: under full load. idle的时候比别人工作还要费电!
: Unfortunately, things aren't as rosy on the power consumption front, as
: Medfield is allegedly consuming an estimated 2.6 watts when idle, and 3.6
: watts when weighed down by a 720p Flash video
: http://www.theverge.com/2011/12/27/2664454/intel-medfield-table
是不是只能等tri-gate 20nm了?
【在 s******v 的大作中提到】
: 干,intel出的什么玩意啊?idle 2.6w!! full function 3.6w. vs. tegra 3 <2w
: under full load. idle的时候比别人工作还要费电!
: Unfortunately, things aren't as rosy on the power consumption front, as
: Medfield is allegedly consuming an estimated 2.6 watts when idle, and 3.6
: watts when weighed down by a 720p Flash video
: http://www.theverge.com/2011/12/27/2664454/intel-medfield-table
g*g
48 楼
Basically a RISC instruction set (like ARM using) has simpler
architecture and it's easier to optimize on other aspects due
to its simpleness. On the other hand, CISC design is more
powerful on the same frenquency but drain battery faster.
Obviously, mobile devices need a better balance than PC. And
the varible frequency/CPU approach of tegra 3 may be the way
to go. It will take many years for intel to catch.
【在 a***e 的大作中提到】
:
: what is wrong with x86, specifically?
: x86 coming from days when memory was very expensive.
: it could make dense and efficient codes.
architecture and it's easier to optimize on other aspects due
to its simpleness. On the other hand, CISC design is more
powerful on the same frenquency but drain battery faster.
Obviously, mobile devices need a better balance than PC. And
the varible frequency/CPU approach of tegra 3 may be the way
to go. It will take many years for intel to catch.
【在 a***e 的大作中提到】
:
: what is wrong with x86, specifically?
: x86 coming from days when memory was very expensive.
: it could make dense and efficient codes.
G*h
52 楼
老皇历了
x86 也就指令编码是 CISC
CPU 内部指令译码之后体系结构跟 RISC 没啥大区别
Atom Z670 跟 ARM 功耗已经差不多了
而且降频技术从 speedstep 就有了
intel 不可能不如 ARM
【在 g*****g 的大作中提到】
: Basically a RISC instruction set (like ARM using) has simpler
: architecture and it's easier to optimize on other aspects due
: to its simpleness. On the other hand, CISC design is more
: powerful on the same frenquency but drain battery faster.
: Obviously, mobile devices need a better balance than PC. And
: the varible frequency/CPU approach of tegra 3 may be the way
: to go. It will take many years for intel to catch.
x86 也就指令编码是 CISC
CPU 内部指令译码之后体系结构跟 RISC 没啥大区别
Atom Z670 跟 ARM 功耗已经差不多了
而且降频技术从 speedstep 就有了
intel 不可能不如 ARM
【在 g*****g 的大作中提到】
: Basically a RISC instruction set (like ARM using) has simpler
: architecture and it's easier to optimize on other aspects due
: to its simpleness. On the other hand, CISC design is more
: powerful on the same frenquency but drain battery faster.
: Obviously, mobile devices need a better balance than PC. And
: the varible frequency/CPU approach of tegra 3 may be the way
: to go. It will take many years for intel to catch.
G*h
54 楼
整机耗电多少?
CPU 多这么 1w 2w 关系大么
【在 s******v 的大作中提到】
: 干,intel出的什么玩意啊?idle 2.6w!! full function 3.6w. vs. tegra 3 <2w
: under full load. idle的时候比别人工作还要费电!
: Unfortunately, things aren't as rosy on the power consumption front, as
: Medfield is allegedly consuming an estimated 2.6 watts when idle, and 3.6
: watts when weighed down by a 720p Flash video
: http://www.theverge.com/2011/12/27/2664454/intel-medfield-table
CPU 多这么 1w 2w 关系大么
【在 s******v 的大作中提到】
: 干,intel出的什么玩意啊?idle 2.6w!! full function 3.6w. vs. tegra 3 <2w
: under full load. idle的时候比别人工作还要费电!
: Unfortunately, things aren't as rosy on the power consumption front, as
: Medfield is allegedly consuming an estimated 2.6 watts when idle, and 3.6
: watts when weighed down by a 720p Flash video
: http://www.theverge.com/2011/12/27/2664454/intel-medfield-table
X*s
58 楼
好虫,你说说CPU是如何消耗电的吧,lol
【在 g*****g 的大作中提到】
: Basically a RISC instruction set (like ARM using) has simpler
: architecture and it's easier to optimize on other aspects due
: to its simpleness. On the other hand, CISC design is more
: powerful on the same frenquency but drain battery faster.
: Obviously, mobile devices need a better balance than PC. And
: the varible frequency/CPU approach of tegra 3 may be the way
: to go. It will take many years for intel to catch.
【在 g*****g 的大作中提到】
: Basically a RISC instruction set (like ARM using) has simpler
: architecture and it's easier to optimize on other aspects due
: to its simpleness. On the other hand, CISC design is more
: powerful on the same frenquency but drain battery faster.
: Obviously, mobile devices need a better balance than PC. And
: the varible frequency/CPU approach of tegra 3 may be the way
: to go. It will take many years for intel to catch.
a*e
59 楼
the risc argument is not really count here. X86 nowadays has a risc pipe
decoder part only take 5% of transistor counts.
everyone is using variable frequency now. I7 could change from 1/2 to 1.2 of
norminal freq for desktop
the laptop version could go down to 33%
【在 g*****g 的大作中提到】
: Basically a RISC instruction set (like ARM using) has simpler
: architecture and it's easier to optimize on other aspects due
: to its simpleness. On the other hand, CISC design is more
: powerful on the same frenquency but drain battery faster.
: Obviously, mobile devices need a better balance than PC. And
: the varible frequency/CPU approach of tegra 3 may be the way
: to go. It will take many years for intel to catch.
a*e
60 楼
arm should run around 250mw/core/GHZ
tegra3 should be around 2W when loaded.
x86 CPU might need an new CPU state for idling.
some changes might be necessary for cache and clock generation.
arm should be patents in these fronts.
intel
【在 s******v 的大作中提到】
: 这个是整机耗电,我如果记得不错的话,arm soc的耗电多在几百mw左右。关键是intel
: 的idle太高了,要是这个数字的话,待机可能连一天都没有。
tegra3 should be around 2W when loaded.
x86 CPU might need an new CPU state for idling.
some changes might be necessary for cache and clock generation.
arm should be patents in these fronts.
intel
【在 s******v 的大作中提到】
: 这个是整机耗电,我如果记得不错的话,arm soc的耗电多在几百mw左右。关键是intel
: 的idle太高了,要是这个数字的话,待机可能连一天都没有。
g*g
61 楼
Even there's no patent issues, it'd take years to play catchup.
I can see Intel making improvements on ultrabook, but unlikely
to shake ARM.
【在 a***e 的大作中提到】
: arm should run around 250mw/core/GHZ
: tegra3 should be around 2W when loaded.
: x86 CPU might need an new CPU state for idling.
: some changes might be necessary for cache and clock generation.
: arm should be patents in these fronts.
:
: intel
I can see Intel making improvements on ultrabook, but unlikely
to shake ARM.
【在 a***e 的大作中提到】
: arm should run around 250mw/core/GHZ
: tegra3 should be around 2W when loaded.
: x86 CPU might need an new CPU state for idling.
: some changes might be necessary for cache and clock generation.
: arm should be patents in these fronts.
:
: intel
s*c
63 楼
risc cisc 之争还没有什么定论 另外当代cpu都有双方融合的影子
现在的x86跟以前的x86也大不一样
【在 g*****g 的大作中提到】
: Basically a RISC instruction set (like ARM using) has simpler
: architecture and it's easier to optimize on other aspects due
: to its simpleness. On the other hand, CISC design is more
: powerful on the same frenquency but drain battery faster.
: Obviously, mobile devices need a better balance than PC. And
: the varible frequency/CPU approach of tegra 3 may be the way
: to go. It will take many years for intel to catch.
现在的x86跟以前的x86也大不一样
【在 g*****g 的大作中提到】
: Basically a RISC instruction set (like ARM using) has simpler
: architecture and it's easier to optimize on other aspects due
: to its simpleness. On the other hand, CISC design is more
: powerful on the same frenquency but drain battery faster.
: Obviously, mobile devices need a better balance than PC. And
: the varible frequency/CPU approach of tegra 3 may be the way
: to go. It will take many years for intel to catch.
d*a
65 楼
没有这么简单。第一呢,Intel的那个hardware translator是个能耗大的东东。
在高性能处理器上不显眼,放在mobile processor上表现就很明显了。
第二呢,ARM或别的RISC处理器,运行的是compiler优化过的指令。RISC架构
的设计,一个很大的考虑,就是要利于compiler的指令优化。优化代码和非优化
代码,可以有两倍到十倍之间的性能和能耗的差别。
x86处理器也用优化compiler,但compiler只能在CISC层面进行指令优化,优化
性能上差了很多。CISC的设计,一开始就不强调对compiler优化的支持。
在高性能处理器上,这个差别显得不大,因为那些处理器有乱序执行和大指令窗
口,动态地再优化一次执行次序。但乱序执行和大指令窗口,代价是更多的耗能,
在mobile processor是不能用的。
所以简单地说,x86架框有先天不足,在能耗上和ARM的差距是无法消除的,这
是我个人的观点。
of
【在 a***e 的大作中提到】
: arm should run around 250mw/core/GHZ
: tegra3 should be around 2W when loaded.
: x86 CPU might need an new CPU state for idling.
: some changes might be necessary for cache and clock generation.
: arm should be patents in these fronts.
:
: intel
在高性能处理器上不显眼,放在mobile processor上表现就很明显了。
第二呢,ARM或别的RISC处理器,运行的是compiler优化过的指令。RISC架构
的设计,一个很大的考虑,就是要利于compiler的指令优化。优化代码和非优化
代码,可以有两倍到十倍之间的性能和能耗的差别。
x86处理器也用优化compiler,但compiler只能在CISC层面进行指令优化,优化
性能上差了很多。CISC的设计,一开始就不强调对compiler优化的支持。
在高性能处理器上,这个差别显得不大,因为那些处理器有乱序执行和大指令窗
口,动态地再优化一次执行次序。但乱序执行和大指令窗口,代价是更多的耗能,
在mobile processor是不能用的。
所以简单地说,x86架框有先天不足,在能耗上和ARM的差距是无法消除的,这
是我个人的观点。
of
【在 a***e 的大作中提到】
: arm should run around 250mw/core/GHZ
: tegra3 should be around 2W when loaded.
: x86 CPU might need an new CPU state for idling.
: some changes might be necessary for cache and clock generation.
: arm should be patents in these fronts.
:
: intel
a*e
66 楼
don't make what you think sound like truth.
you certainly overestimate the compiler optimization. 2x to what?
could you point out which part in arm is designed for compiler optimization?
the decoder is of 5% transistor counts and it won't consume much more than
that.
once you going into super scaler and high frequency, out of order execution
and branch prediction are must and no get away from there. This has nothing
to do with risc or cisc. All latest arm have these feature in some way and
you can't
get away with compiler optimization.
【在 d***a 的大作中提到】
: 没有这么简单。第一呢,Intel的那个hardware translator是个能耗大的东东。
: 在高性能处理器上不显眼,放在mobile processor上表现就很明显了。
: 第二呢,ARM或别的RISC处理器,运行的是compiler优化过的指令。RISC架构
: 的设计,一个很大的考虑,就是要利于compiler的指令优化。优化代码和非优化
: 代码,可以有两倍到十倍之间的性能和能耗的差别。
: x86处理器也用优化compiler,但compiler只能在CISC层面进行指令优化,优化
: 性能上差了很多。CISC的设计,一开始就不强调对compiler优化的支持。
: 在高性能处理器上,这个差别显得不大,因为那些处理器有乱序执行和大指令窗
: 口,动态地再优化一次执行次序。但乱序执行和大指令窗口,代价是更多的耗能,
: 在mobile processor是不能用的。
d*a
67 楼
1. 5% transistor is NOT 5% power consumption.
2. Intel Atom avoids out-of-order execution for saving power. You want a
processor that consumes more power than Atom on a cell phone?
Even if out-of-order is used somehow, it cannot have a large instruction
window as on i3/i5/i7.
3. RISC vs CISC: Too basic to explain. Large architecture register file,
simple
memory addressing, etc, if you want a couple of reasons.
optimization?
execution
nothing
【在 a***e 的大作中提到】
:
: don't make what you think sound like truth.
: you certainly overestimate the compiler optimization. 2x to what?
: could you point out which part in arm is designed for compiler optimization?
: the decoder is of 5% transistor counts and it won't consume much more than
: that.
: once you going into super scaler and high frequency, out of order execution
: and branch prediction are must and no get away from there. This has nothing
: to do with risc or cisc. All latest arm have these feature in some way and
: you can't
2. Intel Atom avoids out-of-order execution for saving power. You want a
processor that consumes more power than Atom on a cell phone?
Even if out-of-order is used somehow, it cannot have a large instruction
window as on i3/i5/i7.
3. RISC vs CISC: Too basic to explain. Large architecture register file,
simple
memory addressing, etc, if you want a couple of reasons.
optimization?
execution
nothing
【在 a***e 的大作中提到】
:
: don't make what you think sound like truth.
: you certainly overestimate the compiler optimization. 2x to what?
: could you point out which part in arm is designed for compiler optimization?
: the decoder is of 5% transistor counts and it won't consume much more than
: that.
: once you going into super scaler and high frequency, out of order execution
: and branch prediction are must and no get away from there. This has nothing
: to do with risc or cisc. All latest arm have these feature in some way and
: you can't
a*e
68 楼
a*e
69 楼
1. it won't be much more than 5% either.
2. A9 and A15 both have ooe. no body how good it would be. but once you get
4 pipelines to feed, no choice there, unless you streaming all the time.
3. nowaday intel cpu has register file as big as any risc, if not bigger.
simple memory addressing result in less dense coding.
simpler design lead to less instruction efficiency.
nothing is free here.
the reality is all CPU kind of merging to the middle ground,
with RISC CPUs like POWER adding all kind of funcy addressing mode
and intel now more or less has a RISC core.
【在 d***a 的大作中提到】
: 1. 5% transistor is NOT 5% power consumption.
: 2. Intel Atom avoids out-of-order execution for saving power. You want a
: processor that consumes more power than Atom on a cell phone?
: Even if out-of-order is used somehow, it cannot have a large instruction
: window as on i3/i5/i7.
: 3. RISC vs CISC: Too basic to explain. Large architecture register file,
: simple
: memory addressing, etc, if you want a couple of reasons.
:
: optimization?
2. A9 and A15 both have ooe. no body how good it would be. but once you get
4 pipelines to feed, no choice there, unless you streaming all the time.
3. nowaday intel cpu has register file as big as any risc, if not bigger.
simple memory addressing result in less dense coding.
simpler design lead to less instruction efficiency.
nothing is free here.
the reality is all CPU kind of merging to the middle ground,
with RISC CPUs like POWER adding all kind of funcy addressing mode
and intel now more or less has a RISC core.
【在 d***a 的大作中提到】
: 1. 5% transistor is NOT 5% power consumption.
: 2. Intel Atom avoids out-of-order execution for saving power. You want a
: processor that consumes more power than Atom on a cell phone?
: Even if out-of-order is used somehow, it cannot have a large instruction
: window as on i3/i5/i7.
: 3. RISC vs CISC: Too basic to explain. Large architecture register file,
: simple
: memory addressing, etc, if you want a couple of reasons.
:
: optimization?
i*o
70 楼
那intel用最好的工艺,造出来的peocessor却比arm耗更多的电,怎么解释?
get
【在 a***e 的大作中提到】
: 1. it won't be much more than 5% either.
: 2. A9 and A15 both have ooe. no body how good it would be. but once you get
: 4 pipelines to feed, no choice there, unless you streaming all the time.
: 3. nowaday intel cpu has register file as big as any risc, if not bigger.
: simple memory addressing result in less dense coding.
: simpler design lead to less instruction efficiency.
: nothing is free here.
: the reality is all CPU kind of merging to the middle ground,
: with RISC CPUs like POWER adding all kind of funcy addressing mode
: and intel now more or less has a RISC core.
get
【在 a***e 的大作中提到】
: 1. it won't be much more than 5% either.
: 2. A9 and A15 both have ooe. no body how good it would be. but once you get
: 4 pipelines to feed, no choice there, unless you streaming all the time.
: 3. nowaday intel cpu has register file as big as any risc, if not bigger.
: simple memory addressing result in less dense coding.
: simpler design lead to less instruction efficiency.
: nothing is free here.
: the reality is all CPU kind of merging to the middle ground,
: with RISC CPUs like POWER adding all kind of funcy addressing mode
: and intel now more or less has a RISC core.
T*n
71 楼
还是列点数据更能说明问题
intel Medfield(Atom Z2460)单核
Clk freq. Power
1.6-GHz ~750-mW
1.3-GHz ~500-mW
600-MHz ~175-mW
100-MHz ~ 50-mW
zero ~ 1 to 18-mW**
图:tegra3 vs Ti omap4 vs QC 8x60
intel Medfield(Atom Z2460)单核
Clk freq. Power
1.6-GHz ~750-mW
1.3-GHz ~500-mW
600-MHz ~175-mW
100-MHz ~ 50-mW
zero ~ 1 to 18-mW**
图:tegra3 vs Ti omap4 vs QC 8x60
T*n
72 楼
性能(from engadget user)
Caffeinemark 3 Benchmark:
Intel Medfield 10500
Nvidia Tegra 2 7500
Qualcomm Snapdragon MSM8260 8000
Samsung Exynos 8500
【在 T****n 的大作中提到】
: 还是列点数据更能说明问题
: intel Medfield(Atom Z2460)单核
: Clk freq. Power
: 1.6-GHz ~750-mW
: 1.3-GHz ~500-mW
: 600-MHz ~175-mW
: 100-MHz ~ 50-mW
: zero ~ 1 to 18-mW**
: 图:tegra3 vs Ti omap4 vs QC 8x60
Caffeinemark 3 Benchmark:
Intel Medfield 10500
Nvidia Tegra 2 7500
Qualcomm Snapdragon MSM8260 8000
Samsung Exynos 8500
【在 T****n 的大作中提到】
: 还是列点数据更能说明问题
: intel Medfield(Atom Z2460)单核
: Clk freq. Power
: 1.6-GHz ~750-mW
: 1.3-GHz ~500-mW
: 600-MHz ~175-mW
: 100-MHz ~ 50-mW
: zero ~ 1 to 18-mW**
: 图:tegra3 vs Ti omap4 vs QC 8x60
d*a
73 楼
这个5%的说法,没有什么意义。处理器上各个logic block之间,
活动程度不一,power density差别很大。Hardware translator
是比较active的部件之一,绝大多数cycle都要工作。
Transistor的动态耗能,只有在部件工作时会产生,所以看静态
的transistor count,方法上是错的。
A9上的OOO,instruction window小,是相当有限的OOO。
Intel的physical register file很大,但architecture register file小。
编译器只能针对architecture register file优化,physical register
file编译器是无法用到的。
POWER的addressing mode哪儿fancy了?展开说说?
get
【在 a***e 的大作中提到】
: 1. it won't be much more than 5% either.
: 2. A9 and A15 both have ooe. no body how good it would be. but once you get
: 4 pipelines to feed, no choice there, unless you streaming all the time.
: 3. nowaday intel cpu has register file as big as any risc, if not bigger.
: simple memory addressing result in less dense coding.
: simpler design lead to less instruction efficiency.
: nothing is free here.
: the reality is all CPU kind of merging to the middle ground,
: with RISC CPUs like POWER adding all kind of funcy addressing mode
: and intel now more or less has a RISC core.
活动程度不一,power density差别很大。Hardware translator
是比较active的部件之一,绝大多数cycle都要工作。
Transistor的动态耗能,只有在部件工作时会产生,所以看静态
的transistor count,方法上是错的。
A9上的OOO,instruction window小,是相当有限的OOO。
Intel的physical register file很大,但architecture register file小。
编译器只能针对architecture register file优化,physical register
file编译器是无法用到的。
POWER的addressing mode哪儿fancy了?展开说说?
get
【在 a***e 的大作中提到】
: 1. it won't be much more than 5% either.
: 2. A9 and A15 both have ooe. no body how good it would be. but once you get
: 4 pipelines to feed, no choice there, unless you streaming all the time.
: 3. nowaday intel cpu has register file as big as any risc, if not bigger.
: simple memory addressing result in less dense coding.
: simpler design lead to less instruction efficiency.
: nothing is free here.
: the reality is all CPU kind of merging to the middle ground,
: with RISC CPUs like POWER adding all kind of funcy addressing mode
: and intel now more or less has a RISC core.
z*n
77 楼
这个东西我有些hand-on经验.
CPU里面很大的一部分是L2 cache,指令流水浮点流水全加起来可能也不如那个大傻
cache大.
CPU能耗设计是一方面, 工艺也有很大影响. 从设计到工艺, Intel都是很NB的, 砸了这
么多年的钱不是闹着玩的.
Intel以前的问题是SoC设计起步太晚, 人家一片解决问题, 你搞个CPU加一堆乱七八糟
的芯片就没法玩了, 现在Medfield/CloverTail没track, 不知道变成什么样子了.
CISC/RISC trade-off 是译码(指令到微码)复杂程度, 过了这一步后面大家差别不大.
CISC指令效率高, 相对来说instruction cache需求小, 但译码困难(导致流水线长? 这
个我也没搞明白为什么有相关性, 也许只是设计选择).
compiler指令优化应当是和这个没有什么关系. x86和ARM都很多代了, 即便以前有设计
问题(其实我认为CISC不强调指令优化是伪命题, 不过没有数据)现在也很可能和当前的
问题不一样. compiler现在早就不是在优化哪有个cycle能塞几个指令了, 往指令流水
里一扔加上各种各样的访存就面目全非了. local optimization也许可以做, 大家用的
技术其实是一样的. 再往上怎样全局优化, 减少cache miss, 大家碰到的问题也差不多
, 没有什么谁领先谁的问题.
同频ARM慢更多是CPU的设计选择. ARM本来就没有什么laptop/desktop市场, niche
market就是低功耗低成本低性能的嵌入市场. RISC本身没有速度问题, 可能需要多一些
instruction cache/registers, 从当前工艺这些都是小问题.
【在 d***a 的大作中提到】
: 没有这么简单。第一呢,Intel的那个hardware translator是个能耗大的东东。
: 在高性能处理器上不显眼,放在mobile processor上表现就很明显了。
: 第二呢,ARM或别的RISC处理器,运行的是compiler优化过的指令。RISC架构
: 的设计,一个很大的考虑,就是要利于compiler的指令优化。优化代码和非优化
: 代码,可以有两倍到十倍之间的性能和能耗的差别。
: x86处理器也用优化compiler,但compiler只能在CISC层面进行指令优化,优化
: 性能上差了很多。CISC的设计,一开始就不强调对compiler优化的支持。
: 在高性能处理器上,这个差别显得不大,因为那些处理器有乱序执行和大指令窗
: 口,动态地再优化一次执行次序。但乱序执行和大指令窗口,代价是更多的耗能,
: 在mobile processor是不能用的。
CPU里面很大的一部分是L2 cache,指令流水浮点流水全加起来可能也不如那个大傻
cache大.
CPU能耗设计是一方面, 工艺也有很大影响. 从设计到工艺, Intel都是很NB的, 砸了这
么多年的钱不是闹着玩的.
Intel以前的问题是SoC设计起步太晚, 人家一片解决问题, 你搞个CPU加一堆乱七八糟
的芯片就没法玩了, 现在Medfield/CloverTail没track, 不知道变成什么样子了.
CISC/RISC trade-off 是译码(指令到微码)复杂程度, 过了这一步后面大家差别不大.
CISC指令效率高, 相对来说instruction cache需求小, 但译码困难(导致流水线长? 这
个我也没搞明白为什么有相关性, 也许只是设计选择).
compiler指令优化应当是和这个没有什么关系. x86和ARM都很多代了, 即便以前有设计
问题(其实我认为CISC不强调指令优化是伪命题, 不过没有数据)现在也很可能和当前的
问题不一样. compiler现在早就不是在优化哪有个cycle能塞几个指令了, 往指令流水
里一扔加上各种各样的访存就面目全非了. local optimization也许可以做, 大家用的
技术其实是一样的. 再往上怎样全局优化, 减少cache miss, 大家碰到的问题也差不多
, 没有什么谁领先谁的问题.
同频ARM慢更多是CPU的设计选择. ARM本来就没有什么laptop/desktop市场, niche
market就是低功耗低成本低性能的嵌入市场. RISC本身没有速度问题, 可能需要多一些
instruction cache/registers, 从当前工艺这些都是小问题.
【在 d***a 的大作中提到】
: 没有这么简单。第一呢,Intel的那个hardware translator是个能耗大的东东。
: 在高性能处理器上不显眼,放在mobile processor上表现就很明显了。
: 第二呢,ARM或别的RISC处理器,运行的是compiler优化过的指令。RISC架构
: 的设计,一个很大的考虑,就是要利于compiler的指令优化。优化代码和非优化
: 代码,可以有两倍到十倍之间的性能和能耗的差别。
: x86处理器也用优化compiler,但compiler只能在CISC层面进行指令优化,优化
: 性能上差了很多。CISC的设计,一开始就不强调对compiler优化的支持。
: 在高性能处理器上,这个差别显得不大,因为那些处理器有乱序执行和大指令窗
: 口,动态地再优化一次执行次序。但乱序执行和大指令窗口,代价是更多的耗能,
: 在mobile processor是不能用的。
a*e
81 楼
for regular CPU, they don't gate clocking agressive enough.
they don't have enough low power saving state. e.g. i5 laptop CPU only
downclocking to 33% and doesn't turn off anything even some of them are not
in use.
apparently in the new atom, the CPU could downclocking all the way to 100MHZ
and even no clocking and sleep by saving the states in RAM, quite crazy way.
it also turns off clocking to unused parts as much as possible.
it is more of a power design issue rather than x86 instruction set issue.
low power x86 used in all kind of embedded before until they quit.
this mobile chip business is high volume low profit margin.
it would be interesting to see how intel is going to play well in such
market
【在 i*****o 的大作中提到】
: 那intel用最好的工艺,造出来的peocessor却比arm耗更多的电,怎么解释?
:
: get
they don't have enough low power saving state. e.g. i5 laptop CPU only
downclocking to 33% and doesn't turn off anything even some of them are not
in use.
apparently in the new atom, the CPU could downclocking all the way to 100MHZ
and even no clocking and sleep by saving the states in RAM, quite crazy way.
it also turns off clocking to unused parts as much as possible.
it is more of a power design issue rather than x86 instruction set issue.
low power x86 used in all kind of embedded before until they quit.
this mobile chip business is high volume low profit margin.
it would be interesting to see how intel is going to play well in such
market
【在 i*****o 的大作中提到】
: 那intel用最好的工艺,造出来的peocessor却比arm耗更多的电,怎么解释?
:
: get
s*u
82 楼
intel reference design的数字已经出来了。
http://www.anandtech.com/show/5365/intels-medfield-atom-z2460-a
【在 d***a 的大作中提到】
: 没有这么简单。第一呢,Intel的那个hardware translator是个能耗大的东东。
: 在高性能处理器上不显眼,放在mobile processor上表现就很明显了。
: 第二呢,ARM或别的RISC处理器,运行的是compiler优化过的指令。RISC架构
: 的设计,一个很大的考虑,就是要利于compiler的指令优化。优化代码和非优化
: 代码,可以有两倍到十倍之间的性能和能耗的差别。
: x86处理器也用优化compiler,但compiler只能在CISC层面进行指令优化,优化
: 性能上差了很多。CISC的设计,一开始就不强调对compiler优化的支持。
: 在高性能处理器上,这个差别显得不大,因为那些处理器有乱序执行和大指令窗
: 口,动态地再优化一次执行次序。但乱序执行和大指令窗口,代价是更多的耗能,
: 在mobile processor是不能用的。
http://www.anandtech.com/show/5365/intels-medfield-atom-z2460-a
【在 d***a 的大作中提到】
: 没有这么简单。第一呢,Intel的那个hardware translator是个能耗大的东东。
: 在高性能处理器上不显眼,放在mobile processor上表现就很明显了。
: 第二呢,ARM或别的RISC处理器,运行的是compiler优化过的指令。RISC架构
: 的设计,一个很大的考虑,就是要利于compiler的指令优化。优化代码和非优化
: 代码,可以有两倍到十倍之间的性能和能耗的差别。
: x86处理器也用优化compiler,但compiler只能在CISC层面进行指令优化,优化
: 性能上差了很多。CISC的设计,一开始就不强调对compiler优化的支持。
: 在高性能处理器上,这个差别显得不大,因为那些处理器有乱序执行和大指令窗
: 口,动态地再优化一次执行次序。但乱序执行和大指令窗口,代价是更多的耗能,
: 在mobile processor是不能用的。
a*e
83 楼
当然不一样,但是晶体管利用率是半导体生命线,没人没事放一堆在那闲着
再说,现在decoder也用cache,不是总要工作的。
decoder本质上干查表的活,活动程度还比不上scheduler.
【在 d***a 的大作中提到】
: 这个5%的说法,没有什么意义。处理器上各个logic block之间,
: 活动程度不一,power density差别很大。Hardware translator
: 是比较active的部件之一,绝大多数cycle都要工作。
: Transistor的动态耗能,只有在部件工作时会产生,所以看静态
: 的transistor count,方法上是错的。
: A9上的OOO,instruction window小,是相当有限的OOO。
: Intel的physical register file很大,但architecture register file小。
: 编译器只能针对architecture register file优化,physical register
: file编译器是无法用到的。
: POWER的addressing mode哪儿fancy了?展开说说?
再说,现在decoder也用cache,不是总要工作的。
decoder本质上干查表的活,活动程度还比不上scheduler.
【在 d***a 的大作中提到】
: 这个5%的说法,没有什么意义。处理器上各个logic block之间,
: 活动程度不一,power density差别很大。Hardware translator
: 是比较active的部件之一,绝大多数cycle都要工作。
: Transistor的动态耗能,只有在部件工作时会产生,所以看静态
: 的transistor count,方法上是错的。
: A9上的OOO,instruction window小,是相当有限的OOO。
: Intel的physical register file很大,但architecture register file小。
: 编译器只能针对architecture register file优化,physical register
: file编译器是无法用到的。
: POWER的addressing mode哪儿fancy了?展开说说?
d*a
85 楼
Intel的微结构(microarchitecture)和工艺一直很厉害,做出
这个性能,其实也是意料之中的。但它已经用上32nm了,A5
是45nm。
【在 s**u 的大作中提到】
: intel reference design的数字已经出来了。
: http://www.anandtech.com/show/5365/intels-medfield-atom-z2460-a
这个性能,其实也是意料之中的。但它已经用上32nm了,A5
是45nm。
【在 s**u 的大作中提到】
: intel reference design的数字已经出来了。
: http://www.anandtech.com/show/5365/intels-medfield-atom-z2460-a
a*e
86 楼
Z系32bit的没有OOO,丫就靠HT来填空泡
A9倒是OOO,不过看起来效率不高
cache对GHZ的CPU性能影响太大,layout又简单,没办法的事
decoder其实是pipeline的一部分,不比其他逻辑块更忙
A9也是decoder->scheduler->execution的结构
这年头就没有直接执行bin的,流水线后都靠decoder
转成微码再执行,这样资源复用率更高
A9也就是decoder比X86简单点
微码都是对各自的ISA优化过的
这里没有翻译器的事情
【在 d***a 的大作中提到】
: L2/L3 cache,不就是很多时候闲着吗。要是所有的部件都象
: hw translator那样忙,电池能支撑多久。
: 现在的处理器,哪有让它所有部件全时peak状态运行的。能关
: 的部件都要关掉,能节能的都要省下来。但hw translator无法关,
: 每条指令都要用它,没什么节能的余地。
: Atom是in-order core,没有ooo scheduler。
A9倒是OOO,不过看起来效率不高
cache对GHZ的CPU性能影响太大,layout又简单,没办法的事
decoder其实是pipeline的一部分,不比其他逻辑块更忙
A9也是decoder->scheduler->execution的结构
这年头就没有直接执行bin的,流水线后都靠decoder
转成微码再执行,这样资源复用率更高
A9也就是decoder比X86简单点
微码都是对各自的ISA优化过的
这里没有翻译器的事情
【在 d***a 的大作中提到】
: L2/L3 cache,不就是很多时候闲着吗。要是所有的部件都象
: hw translator那样忙,电池能支撑多久。
: 现在的处理器,哪有让它所有部件全时peak状态运行的。能关
: 的部件都要关掉,能节能的都要省下来。但hw translator无法关,
: 每条指令都要用它,没什么节能的余地。
: Atom是in-order core,没有ooo scheduler。
d*a
90 楼
micro-op其实并不是micro-code。Micro-op和RISC指令类似。
【在 a***e 的大作中提到】
: Z系32bit的没有OOO,丫就靠HT来填空泡
: A9倒是OOO,不过看起来效率不高
: cache对GHZ的CPU性能影响太大,layout又简单,没办法的事
: decoder其实是pipeline的一部分,不比其他逻辑块更忙
: A9也是decoder->scheduler->execution的结构
: 这年头就没有直接执行bin的,流水线后都靠decoder
: 转成微码再执行,这样资源复用率更高
: A9也就是decoder比X86简单点
: 微码都是对各自的ISA优化过的
: 这里没有翻译器的事情
【在 a***e 的大作中提到】
: Z系32bit的没有OOO,丫就靠HT来填空泡
: A9倒是OOO,不过看起来效率不高
: cache对GHZ的CPU性能影响太大,layout又简单,没办法的事
: decoder其实是pipeline的一部分,不比其他逻辑块更忙
: A9也是decoder->scheduler->execution的结构
: 这年头就没有直接执行bin的,流水线后都靠decoder
: 转成微码再执行,这样资源复用率更高
: A9也就是decoder比X86简单点
: 微码都是对各自的ISA优化过的
: 这里没有翻译器的事情
a*s
95 楼
这么深奥,弄个明白的吧,Intel这个到底能不能干掉ARM和Nvidia?
c*y
97 楼
moto跳了
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