c*h
7 楼
use dll align its negative edge with positive edge. The dll delay is 2n
arcitecture. the phase diff is 180 now. take the signal in the middle, the
the phase diff is 90 now. XOR the two signals, u get T/2. Do one more time,
u get T/4.
maybe there is better idea.
【在 h*****i 的大作中提到】![](/moin_static193/solenoid/img/up.png)
: 有一个时钟,周期是T,怎么设计一个电路产生一个T/4的时钟?
: 想了好久,想用delay,然后异或,但是我事先也不知道它的周期呀。
: 非常感谢!!
arcitecture. the phase diff is 180 now. take the signal in the middle, the
the phase diff is 90 now. XOR the two signals, u get T/2. Do one more time,
u get T/4.
maybe there is better idea.
【在 h*****i 的大作中提到】
![](/moin_static193/solenoid/img/up.png)
: 有一个时钟,周期是T,怎么设计一个电路产生一个T/4的时钟?
: 想了好久,想用delay,然后异或,但是我事先也不知道它的周期呀。
: 非常感谢!!
j*j
8 楼
en, althrough it is not the precisely T/4, but should be OK for normal
application.
but make sure the delay line can be locked, which means you should know T is
in some range so that you know how many delay cells you should put in the
delay line.
,
【在 c******h 的大作中提到】![](/moin_static193/solenoid/img/up.png)
: use dll align its negative edge with positive edge. The dll delay is 2n
: arcitecture. the phase diff is 180 now. take the signal in the middle, the
: the phase diff is 90 now. XOR the two signals, u get T/2. Do one more time,
: u get T/4.
: maybe there is better idea.
application.
but make sure the delay line can be locked, which means you should know T is
in some range so that you know how many delay cells you should put in the
delay line.
,
【在 c******h 的大作中提到】
![](/moin_static193/solenoid/img/up.png)
: use dll align its negative edge with positive edge. The dll delay is 2n
: arcitecture. the phase diff is 180 now. take the signal in the middle, the
: the phase diff is 90 now. XOR the two signals, u get T/2. Do one more time,
: u get T/4.
: maybe there is better idea.
h*i
15 楼
看来只有DLL了,我在网上也找不到DLL的 verilog codes.请问哪位有呀?非常感谢,
急用呀。
急用呀。
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