s*o
2 楼
积攒人品。高通招聘senior 硬件工程师。地点在湾区。要求做过multimedia IP。最好
有工作经历。
有兴趣发简历到[email protected]/* */。为避免争议,提前声明,不是所有简历都会
内推,如果合适会和你联系。
As an ASIC Design Engineer, you will be responsible for digital signal
processing HW designs, specifically data path as well as control intensive
digital designs. You will work with the architects of Systems, as well as
other SoC team ASIC designers and SW engineers to micro-architect and
implement designs specific to Digital Sensor subsystems for integration into
SoC for mobile applications.
Required: At least 8 years of work experience in the following areas: - RTL
design experience on-chip with custom digital logic - Synopsys Design
Compiler tool for synthesizing RTL and use of simulation tools - C/C++,
System Verilog, System C & Matlab, Tcl/Perl/shell-scripting skills - Any of
the following HLS tools: Catapult, Cadence C-to-Silicon, Forte / Cadence
Cynthesizer, or Cadence Stratus - Design Rule Checking and Clock Domain
Crossing checks
Preferred Qualifications - FPGA experience - Experience with sensor data
processing - Gate level Simulation bring up and usage of power extraction
tools
有工作经历。
有兴趣发简历到[email protected]/* */。为避免争议,提前声明,不是所有简历都会
内推,如果合适会和你联系。
As an ASIC Design Engineer, you will be responsible for digital signal
processing HW designs, specifically data path as well as control intensive
digital designs. You will work with the architects of Systems, as well as
other SoC team ASIC designers and SW engineers to micro-architect and
implement designs specific to Digital Sensor subsystems for integration into
SoC for mobile applications.
Required: At least 8 years of work experience in the following areas: - RTL
design experience on-chip with custom digital logic - Synopsys Design
Compiler tool for synthesizing RTL and use of simulation tools - C/C++,
System Verilog, System C & Matlab, Tcl/Perl/shell-scripting skills - Any of
the following HLS tools: Catapult, Cadence C-to-Silicon, Forte / Cadence
Cynthesizer, or Cadence Stratus - Design Rule Checking and Clock Domain
Crossing checks
Preferred Qualifications - FPGA experience - Experience with sensor data
processing - Gate level Simulation bring up and usage of power extraction
tools
C*B
4 楼
8年在求康应该至少staff了,怎么才给sr
难道现如今连title都节省了?
难道现如今连title都节省了?
s*o
6 楼
听经理语气 要求应该不是硬性的 senior或者staff也是根据个人情况
[在 shawndongbo (dd) 的大作中提到:]
:积攒人品。高通招聘senior 硬件工程师。地点在湾区。要求做过multimedia IP。最
好有工作经历。
:有兴趣发简历到[email protected]/* */。为避免争议,提前声明,不是所有简历都会
:...........
[在 shawndongbo (dd) 的大作中提到:]
:积攒人品。高通招聘senior 硬件工程师。地点在湾区。要求做过multimedia IP。最
好有工作经历。
:有兴趣发简历到[email protected]/* */。为避免争议,提前声明,不是所有简历都会
:...........
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