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芯片應該為軟件服務,譬如硬件加速的虛擬內存MMU、虛擬GPU、虛
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芯片應該為軟件服務,譬如硬件加速的虛擬內存MMU、虛擬GPU、虛# Programming - 葵花宝典
m*3
1
都是一些小错误,但老板非常不开心,天天给我脸色看,我也做的好委屈。这是第一份
工作,目前只做了4个月-5个月,该辞职吗?
每天忙的一塌糊涂,老与数字打交道,真的很难不犯错。我已经尽全力了。每天坐在办
公室都觉得害怕,公司一直在招人却没招到。
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m*p
2
剛剛看linux kernel 4.17的patch想到的:
This patch removes the entire architecture code for blackfin, cris, frv,
m32r, metag, mn10300, score, and tile, including the associated device
drivers. In the end, it seems that while the eight architectures are
extremely
different, they all suffered the same fate: There was one company in charge
of an SoC line, a CPU microarchitecture and a software ecosystem, which was
more costly than licensing newer off-the-shelf CPU cores from a third party
(typically ARM, MIPS, or RISC-V). It seems that all the SoC product lines
are still around, but have not used the custom CPU architectures for several
years at this point. In contrast, CPU instruction sets that remain popular
and have actively maintained kernel ports tend to all be used across
multiple licensees.
單獨在硬件軟件垂直畫圈就是死,未來的硬件就不應該物理創新,極限快到了,不用再
跟上帝鬥了。。。
就是玩加速,軟件算法早就有了,就是慢慢慢
芯片應該給特殊軟件提速,反正晶體管目前有的是,但頻率提不上去了。
從遠古時期的MMU,也是先有軟件概念,大家覺得好,然後才上硬件加速MMU。
還有FPU,軟件也可以算,就是慢而已。
GPU其實也可以完全軟件實現,就是遊戲不爽而已。
虛擬IO/APIC的用戶就是網卡啥的,這個其實過去15年intel、vmware投入非常大,也
是硬件加速虛擬化。
下一步就是虛擬學習了,目前AWS還有F1、P3啥的,未來應該統統虛擬化,集成到CPU
SOC裡面。
這裡面最難的其實是抽象出虛擬學習最核心的部分,譬如CPU就是跳轉和加法器,MMU就
是查表。
硬件怎麼買?就是買IP授權,SoC整合廠買IP,然後像組裝PC一樣出CPU,帶各種硬件加
速。
誰想單獨自己上架構、ISA、封閉軟件,商業模式上就是找死。蘋果三星華為那樣的大
公司也是偷偷買IP,魔改。
如果說1950年IBM能出mainframe,啥都自己做,那是從0到1的創新,2000年還有公司那
麼做就是傻。
同理intel在1970年做完全自己的CPU是無奈,那2020年誰敢出封閉的CPU,就是找死。
新興的FLAG做CPU,其實是我說的CPU集成商,按軟件需求組裝硬件加速IP到SOC裡面,
因為他們有錢任性。。。
我認為狗的TPU1/2很快會做成通用IP,集成到CPU裡面。。。目前CPU只有intel架構不
開放,讓我們拭目以待。。。
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g*u
3
努力让自己不犯错啊
这算是对自己的训练阿
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m*p
4
Renesas真是CPU垃圾回收站啊。。。
The Renesas M32R is a 32-bit RISC instruction set architecture (ISA)
developed by Mitsubishi Electric for embedded microprocessors and
microcontrollers. M32R processors are used in embedded systems such as
Engine Control Units, digital cameras and PDAs.
Renesas SuperH (or SH) is a 32-bit reduced instruction set computing (RISC)
instruction set architecture (ISA) developed by Hitachi and currently
produced by Renesas. It is implemented by microcontrollers and
microprocessors for embedded systems. The SH-1 and the SH-2 were used in the
Sega Saturn and Sega 32X. These cores have 16-bit instructions for better
code density than 32-bit instructions, which was a great benefit at the time
, due to the high cost of main memory.
Renesas V850 is the trademark name for a 32-bit RISC CPU architecture of
Renesas Electronics for embedded microcontrollers, introduced in early 90's
by NEC and still being developed as of 2018. The first V850 CPU core was
used for many DVD drives manufactured by NEC Corporation, then Sony Optiarc.
NEC Electronics (currently Renesas Electronics) itself intensively
developed application-specific standard products (ASSPs) for optical disk
drives named SCOMBO® Series. This first generation of processor core
was also used for hard disk drives manufactured by Quantum Corporation.
Renesas RX is the family name for a range of 32-bit CISC microcontrollers
manufactured by Renesas Electronics. RX is an acronym for Renesas Extreme, a
description of the key concept behind the product family, that is "extreme
high performance". The RX family was launched in 2009 by Renesas Technology
with the first product range designated the RX600 series and targeting
applications such as metering, motor control, human machine interfaces (HMI)
, networking, and industrial automation. Since 2009 this MCU family range
has been enlarged with a smaller variant the RX200 series and also through
enhanced performance versions.
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