【 以下文字转载自 Returnee 讨论区 】
发信人: laoaky (laoaky), 信区: Returnee
标 题: 高通内推QUALCOMM 上海 Principal 200KUSD+
发信站: BBS 未名空间站 (Mon Mar 3 03:58:57 2014, 美东)
working place is at Shanghai but with U.S. salary/compensation standard. The
candidate should speak Chinese/Mandarin. Some of the cases you only need
to stay in Shanghai for less than 6 months.
Interested party, please email resume to parkingsv(AT)yahoo.com
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Job description
The candidate will be responsible for the architecture and ASIC design and
co-verification of various 802.11 wireless baseband IPs within current and
next generation wireless products. The candidate will work within the local
DSP/digital development team and closely with system/simulation/verification
/RF engineering teams in US to develop and implement DSP/digital blocks to
build WiFi IPs.
Job responsibilities includes: spec development and design of DSP/digital
blocks, developing co-verification platforms, performing simulations, and
solving integration and testing problems during the development,
characterization, and production stages of the product. Successful candidate
must have the ability to communicate with engineers of various backgrounds:
systems, software, digital hardware, RFIC design, and verification.
• Extensive hands-on experience in the development of WiFi baseband IC
design. The candidate must have at least 8-years development experience on
WiFi 802.11 a/g/b including minimum 3 years on 802.11n/ac.
• Deep knowledge and good understanding of: digital communication
theory, information theory; specifically on: equalization, Fourier transform
, spatial-temporal coding, linear and maximum-likelihood estimation, Viterbi
decoding, frequency/ timing estimation and calibration, automatic gain
control, transmitter beam forming, diversity combining, and their high-speed
DSP/digital implementation.
• Extensive experience with RTL programming languages.
• Experience with verification methodologies and tools and advanced
complex RTL/C test-bench developments. The familiarity with UVM environment
is a plus.
• Experience with developing algorithms in C, C++, and Mat lab.
• Experience with scripting language such as Perl, Python.
• Must have experience with lab testing and characterization of
digital sub-systems.
• Candidate must have strong English communication skills with
willingness to interact with various groups within the company.
• Experience with physical design flows, tools, methodologies, and
development of timing constraints is a plus.
• Familiarity with flows and tools for co-simulation of RTL and C
models is a plus.
• Familiarity with testing and integration of RF and baseband systems
in the lab is a plus.
• Experience with implementation of calibration modules for RF/Analog
blocks is a plus..
• Typically requires a Master degree and 8 years of experience or a
PhD and 5 years, in VLSI/ASIC architecture design or ASIC implementation of
digital signal processing function.
